cyv15g0204rb Cypress Semiconductor Corporation., cyv15g0204rb Datasheet - Page 9

• Manufacturer Part Number: cyv15g0204rb
• Description: Independent Clock Dual Hotlink Ii Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02103 Rev. *B
Pin Definitions
CYV15G0204RB Dual HOTLink II Deserializing Reclocker
DATA[6:0]
RXRATE[A..B]
SDASEL[2..1][A..B]
[1:0]
RXPLLPD[A..B]
RXBIST[A..B][1:0]
ROE2[A..B]
ROE1[A..B]
Factory Test Modes
SCANEN2
TMEN3
ROUTA1±
ROUTB1±
ROUTA2±
ROUTB2±
INA1±
INB1±
INA2±
INB2±
TMS
TCLK
TDO
TDI
TRST
V
GND
Note:
4.
Name
Internal Device Configuration Latches
Analog I/O
JTAG Interface
Power
CC
See Device Configuration and Control Interface for detailed information on the internal latches.
(continued)
Internal Latch
Internal Latch
LVTTL input
asynchronous,
internal pull-up
Internal Latch
Internal Latch
Internal Latch
Internal Latch
LVTTL input,
internal pull-down
LVTTL input,
internal pull-down
CML Differential
Output
CML Differential
Output
Differential Input
Differential Input
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-down
3-State LVTTL
Output
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-up
I/O Characteristics Signal Description
[4]
[4]
[4]
[4]
[4]
[4]
Control Data Bus. The DATA[6:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[6:0] bus into the latch
specified by address location on the ADDR[2:0] bus.
latches within the device, and the initialization value of the latches upon the assertion
of RESET. Table 4 shows how the latches are mapped in the device.
Receive Clock Rate Select.
Signal Detect Amplitude Select.
Receive Channel Power Control.
Receive Bist Disabled.
Reclocker Differential Serial Output Driver 2 Enable.
Reclocker Differential Serial Output Driver 1 Enable.
Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a
NO CONNECT, or GND only.
Primary Differential Serial Data Output. The ROUTx1± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-
compatible connections.
Secondary Differential Serial Data Output. The ROUTx2± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
Primary Differential Serial Data Input. The INx1± input accepts the serial data
stream for deserialization. The INx1± serial stream is passed to the receive CDR
circuit to extract the data content when INSELx = HIGH.
Secondary Differential Serial Data Input. The INx2± input accepts the serial data
stream for deserialization. The INx2± serial stream is passed to the receiver CDR
circuit to extract the data content when INSELx = LOW.
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained
high for ≥5 TCLK cycles, the JTAG test controller is reset.
JTAG Test Clock.
Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not
selected.
Test Data In. JTAG data input port.
JTAG reset signal. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
+3.3V Power.
Signal and Power Ground for all internal circuits.
[3 ]
Table 3 lists the configuration
CYV15G0204RB
Page 9 of 24
[+] Feedback