cyv15g0204rb Cypress Semiconductor Corporation., cyv15g0204rb Datasheet - Page 12

• Manufacturer Part Number: cyv15g0204rb
• Description: Independent Clock Dual Hotlink Ii Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02103 Rev. *B
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on both channels.
BIST Status State Machine
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the {BISTSTx,
RXDx[0], RXDx[1]} bits identify the present state of the BIST
compare operation.
The BIST state machine has multiple states, as shown in
Figure 2 and Table 5. When the receive PLL detects an out-of-
lock condition, the BIST state is forced to the Start-of-BIST
state, regardless of the present state of the BIST state
machine. If the number of detected errors ever exceeds the
number of valid matches by greater than 16, the state machine
is forced to the WAIT_FOR_BIST state where it monitors the
receive path for the first character of the next BIST sequence.
Power Control
The CYV15G0204RB supports user control of the powered up
or down state of each transmit and receive channel. The
receive channels are controlled by the RXPLLPDx latch via the
device configuration interface. When RXPLLPDx = 0, the
associated PLL and analog circuitry of the channel is disabled.
The transmit channels are controlled by the OE1x and the
OE2x latches via the device configuration interface. The
reclocker function is controlled by the ROE1x and the ROE2x
latches via the device configuration interface. When a driver is
disabled via the configuration interface, it is internally powered
down to reduce device power. If both serial drivers for a
channel are in this disabled state, the associated internal logic
for that channel is also powered down. When the reclocker
serial drivers are disabled, the reclocker function will be
disabled, but the deserialization logic and parallel outputs will
remain enabled.
Device Reset State
When the CYV15G0204RB is reset by assertion of RESET, all
state machines, counters, and configuration latches in the
device are initialized to a reset state. See Table 3 for the
initialize values of the configuration latches.
Following a device reset, it is necessary to enable the receive
channels used for normal operation. This can be done by
sequencing the appropriate values on the device configuration
interface.
Device Configuration and Control Interface
The CYV15G0204RB is highly configurable via the configu-
ration interface. The configuration interface allows each
channel to be configured independently. Table 3 lists the
configuration latches within the device including the initial-
ization value of the latches upon the assertion of RESET.
Table 4 shows how the latches are mapped in the device.
Each row in the Table 4 maps to a 7-bit latch bank. There are
6 such write-only latch banks. When WREN = 0, the logic value
in the DATA[6:0] is latched to the latch bank specified by the
values in ADDR[2:0]. The second column of Table 4 specifies
the channels associated with the corresponding latch bank.
For example, the first three latch banks (0,1 and 2) consist of
configuration bits for channel A.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by 2 static and 1 dynamic latch
banks. The S type contain those settings that normally do not
change for a given application, whereas the D type controls
the settings that could change during the application's lifetime.
The first and second rows of each channel (address numbers
0, 1, 5, and 6) are the static control latches. The third row of
latches for each channel (address numbers 2, 7) are the
dynamic control latches that are associated with enabling
dynamic functions within the device. Address numbers 3 and
4 are internal test registers.
Static Latch Values
There are some latches in the table that have a static value (ie.
1, 0, or X). The latches that have a ‘1’ or ‘0’ must be configured
with their corresponding value each time that their associated
latch bank is configured. The latches that have an ‘X’ are don’t
cares and can be configured with any value.
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CYV15G0204RB
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