cyv15g0204rb Cypress Semiconductor Corporation., cyv15g0204rb Datasheet - Page 7

• Manufacturer Part Number: cyv15g0204rb
• Description: Independent Clock Dual Hotlink Ii Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02103 Rev. *B
Pin Definitions
CYV15G0204RB Dual HOTLink II Deserializing Reclocker
RXDA[9:0]
RXDB[9:0]
BISTSTA
BISTSTB
REPDOA
REPDOB
TRGCLKA±
TRGCLKB±
RXCLKA±
RXCLKB±
RECLKOA
RECLKOB
RESET
Name
Receive Path Data and Status Signals
Receive Path Clock Signals
Device Control Signals
LVTTL Output,
synchronous to the
RXCLK± output
LVTTL Output,
synchronous to the
RXCLKx ± output
Asynchronous to
reclocker output
channel
enable / disable
Differential LVPECL
or single-ended
LVTTL input clock
LVTTL Output Clock Receive Clock Output. RXCLKx± is the receive interface clock used to control
LVTTL Output
LVTTL Input,
asynchronous,
internal pull-up
I/O Characteristics Signal Description
Parallel Data Output. RXDx[9:0] parallel data outputs change relative to the receive
interface clock. If RXCLKx± is a full-rate clock, the RXCLKx± clock outputs are
complementary clocks operating at the character rate. The RXDx[9:0] outputs for the
associated receive channels follow rising edge of RXCLKx+ or falling edge of
RXCLKx–. If RXCLKx± is a half-rate clock, the RXCLKx± clock outputs are comple-
mentary clocks operating at half the character rate. The RXDx[9:0] outputs for the
associated receive channels follow both the falling and rising edges of the associated
RXCLKx± clock outputs.
When BIST is enabled on the receive channel, the BIST status is presented on the
RXDx[1:0] and BISTSTx outputs. See Table 5 for each status reported by the BIST
state machine. Also, while BIST is enabled, the RXDx[9:2] outputs should be
ignored.
BIST Status Output. When RXBISTx[1:0] = 10, BISTSTx (along with RXDx[1:0])
displays the status of the BIST reception. See Table 5 for the BIST status reported
for each combination of BISTSTx and RXDx[1:0].
When RXBISTx[1:0] ≠ 10, BISTSTx should be ignored.
Reclocker Powered Down Status Output. REPDOx is asserted HIGH, when the
associated channel’s reclocker output logic is powered down. This occurs when
ROE2x and ROE1x are both disabled by setting ROE2x = 0 and ROE1x = 0.
CDR PLL Training Clock. TRGCLKx± clock inputs are used as the reference source
for the frequency detector (Range Controller) of the associated receive PLL to
reduce PLL acquisition time.
In the presence of valid serial data, the recovered clock output of the receive CDR
PLL (RXCLKx±) has no frequency or phase relationship with TRGCLKx±.
When driven by a single-ended LVCMOS or LVTTL clock source, connect the clock
source to either the true or complement TRGCLKx input, and leave the alternate
TRGCLKx input open (floating). When driven by an LVPECL clock source, the clock
must be a differential clock, using both inputs.
timing of the RXDx[9:0] parallel outputs. These true and complement clocks are used
to control timing of data output transfers. These clocks are output continuously at
either the half-character rate (1/20
serial bit-rate) of the data being received, as selected by RXRATEx.
Reclocker Clock Output. RECLKOx output clock is synthesized by the associated
reclocker output PLL and operates synchronous to the internal recovered character
clock. RECLKOx operates at either the same frequency as RXCLKx± (RXRATEx =
0), or at twice the frequency of RXCLKx± (RXRATEx = 1).The reclocker clock outputs
have no fixed phase relationship to RXCLKx±.
Asynchronous Device Reset. RESET initializes all state machines, counters, and
configuration latches in the device to a known state. RESET must be asserted LOW
for a minimum pulse width. When the reset is removed, all state machines, counters
and configuration latches are at an initial state. See Table 3 for the initialize values
of the device configuration latches.
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the serial bit-rate) or character rate (1/10
CYV15G0204RB
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the
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