cyv15g0204rb Cypress Semiconductor Corporation., cyv15g0204rb Datasheet - Page 10

• Manufacturer Part Number: cyv15g0204rb
• Description: Independent Clock Dual Hotlink Ii Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02103 Rev. *B
CYV15G0204RB HOTLink II Operation
The CYV15G0204RB is a highly configurable, independent
clocking, dual-channel reclocking deserializer designed to
support reliable transfer of large quantities of digital video
data, using high-speed serial links from multiple sources to
multiple destinations. This device supports two 10-bit
channels.
CYV15G0204RB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, INx1± and INx2±, are
available on each channel for accepting serial data streams.
The active Serial Line Receiver on a channel is selected using
the associated INSELx input. The Serial Line Receiver inputs
are differential, and can accommodate wire interconnect and
filtering losses or transmission line attenuation greater than
16 dB. For normal operation, these inputs should receive a
signal of at least VI
differential. Each Line Receiver can be DC- or AC-coupled to
+3.3V powered fiber-optic interface modules (any ECL/PECL
family, not limited to 100K PECL) or AC-coupled to +5V
powered optical modules. The common-mode tolerance of
these line receivers accommodates a wide range of signal
termination voltages. Each receiver provides internal DC-
restoration, to the center of the receiver’s common mode
range, for AC-coupled signals.
Signal Detect/Link Fault
Each selected Line Receiver (i.e., that routed to the clock and
data recovery PLL) is simultaneously monitored for
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each
receive channel, which changes synchronous to the receive
interface clock.
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable to allow
operation with highly attenuated signals, or in high-noise
environments. The analog amplitude level detection is set by
the SDASELx latch via device configuration interface. The
SDASELx latch sets the trip point for the detection of a valid
signal at one of three levels, as listed in Table 1. This control
input affects the analog monitors for both receive channels.
Note:
5.
• analog amplitude above amplitude level selected by
• transition density above the specified limit
• range controls report the received data stream inside
• receive channel enabled
• Presence of reference clock
• ULCx is not asserted.
SDASELx
normal frequency range (±1500
The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals
may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
DIFF
> 100 mV, or 200 mV peak-to-peak
[21]
ppm)
The Analog Signal Detect monitors are active for the Line
Receiver as selected by the associated INSELx input.
Table 1. Analog Amplitude Detect Valid Signal Levels
Transition Density
The Transition Detection logic checks for the absence of
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received, the
Detection logic for that channel asserts LFIx.
Range Controls
The CDR circuit includes logic to monitor the frequency of the
PLL Voltage Controlled Oscillator (VCO) used to sample the
incoming data stream. This logic ensures that the VCO
operates at, or near the rate of the incoming data stream for
two primary cases:
To perform this function, the frequency of the RXPLL VCO is
periodically compared to the frequency of the TRGCLKx±
input. If the VCO is running at a frequency beyond
±1500 ppm
periodically forced to the correct frequency (as defined by
TRGCLKx±, SPDSELx, and TRGRATEx) and then released in
an attempt to lock to the input data stream.
The sampling and relock period of the Range Control is calcu-
lated as follows: RANGE_CONTROL_ SAMPLING_PERIOD
= (RECOVERED BYTE CLOCK PERIOD) * (4096).
During the time that the Range Control forces the RXPLL VCO
to track TRGCLKx±, the LFIx output is asserted LOW. After a
valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx will be HIGH.
The operating serial signaling-rate and allowable range of
TRGCLK± frequencies are listed in Table 2.
Table 2. Operating Speed Settings
SDASEL Typical Signal with Peak Amplitudes Above
• when the incoming data stream resumes after a time in
• when the incoming data stream is outside the acceptable
MID (Open)
SPDSELx
which it has been “missing.”
signaling rate range.
00
01
10
11
HIGH
LOW
Analog Signal Detector is disabled
140 mV p-p differential
280 mV p-p differential
420 mV p-p differential
[21]
as defined by the TRGCLKx± frequency, it is
TRGRATEx
1
0
1
0
1
0
TRGCLKx±
Frequency
reserved
19.5–40
CYV15G0204RB
80–150
(MHz)
20–40
40–80
40–75
Page 10 of 24
Rate (Mbps)
Signaling
800–1500
195–400
400–800
[5]
[+] Feedback