mfrc52301hn1-trayb NXP Semiconductors, mfrc52301hn1-trayb Datasheet - Page 32

• Manufacturer Part Number: mfrc52301hn1-trayb
• Description: Contactless Reader Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
MFRC523_33
Product data sheet
PUBLIC
8.8.1 Hard power-down
8.8.2 Soft Power-down mode
8.8.3 Transmitter Power-down mode
8.8 Power reduction modes
8.9 Oscillator circuit
Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pins and
clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or
LOW level.
Soft Power-down mode is entered immediately after the CommandReg register’s
PowerDown bit is set to logic 1. All internal current sinks are switched off, including the
oscillator buffer. However, the digital input buffers are not separated from the input pins
and keep their functionality. The digital output pins do not change their state.
During soft power-down, all register values, the FIFO buffer content and the configuration
keep their current contents.
After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft Power-down
mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately
clear it. It is cleared automatically by the MFRC523 when Soft Power-down mode is
exited.
Remark: If the internal oscillator is used, you must take into account that it is supplied by
pin AVDD and it will take a certain time (t
cycles can be detected by the internal logic. It is recommended for the serial UART, to first
send the value 55h to the MFRC523. The oscillator must be stable for further access to
the registers. To ensure this, perform a read access to address 0 until the MFRC523
answers to the last read command with the register content of address 0. This indicates
that the MFRC523 is ready.
The Transmitter Power-down mode switches off the internal antenna drivers thereby,
turning off the RF field. Transmitter Power-down mode is entered by setting either the
TxControlReg register’s Tx1RFEn bit or Tx2RFEn bit to logic 0.
Fig 22. Quartz crystal connection
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 5 March 2010
115233
OSCOUT
osc
MFRC523
27.12 MHz
) until the oscillator is stable and the clock
OSCIN
001aal162
Contactless reader IC
MFRC523
© NXP B.V. 2010. All rights reserved.
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