mfrc531 NXP Semiconductors, mfrc531 Datasheet - Page 97

• Manufacturer Part Number: mfrc531
• Description: Iso/iec 14443 Reader Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
MFRC531_34
Product data sheet
PUBLIC
13.4.4 SPI timing
13.4.5 Clock frequency
Table 161. SPI timing specification
Remark: To send more bytes in one data stream the NSS signal must be LOW during the
send process. To send more than one data stream the NSS signal must be HIGH between
each data stream.
The clock input is pin OSCIN.
Table 162. Clock frequency
The clock applied to the MFRC531 acts as a time constant for the synchronous system’s
encoder and decoder. The stability of the clock frequency is an important factor for
ensuring proper performance. To obtain highest performance, clock jitter must be as small
as possible. This is best achieved using the internal oscillator buffer and the
recommended circuitry; see
Symbol
t
t
t
t
t
t
Symbol
f
δ
t
SCKL
SCKH
DSHQX
DQXCH
h(SCKL-Q)
(SCKL-NSSH)
clk
jit
Fig 23. Timing diagram for SPI
clk
MOSI
MISO
SCK
NSS
Parameter
clock frequency
clock duty cycle
jitter time
Parameter
SCK LOW time
SCK HIGH time
data output hold after data strobe
HIGH time
data input/output changing to clock
HIGH time
SCK LOW to data output hold time
SCK LOW to NSS HIGH time
t
SCKL
t
DQXCH
Rev. 3.4 — 26 January 2010
Section 9.8 on page
MSB
MSB
056634
Conditions
checked by the clock
filter
of clock edges
t
DSHQX
t
t
SCKH
h(SCKL-Q)
Conditions
t
29.
SCKL
t
DQXCH
Min
-
40
-
ISO/IEC 14443 reader IC
Typ
13.56
50
-
Min
100
100
20
20
-
20
MFRC531
t
CLSH
© NXP B.V. 2010. All rights reserved.
LSB
LSB
-
-
-
-
-
Typ Max Unit
-
Max
-
60
10
-
-
-
-
15
-
001aaj641
Unit
MHz
%
ps
97 of 116
ns
ns
ns
ns
ns
ns