mfrc531 NXP Semiconductors, mfrc531 Datasheet - Page 15

• Manufacturer Part Number: mfrc531
• Description: Iso/iec 14443 Reader Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 15.
MFRC531_34
Product data sheet
PUBLIC
EEPROM
byte
address
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
Register
address
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
Shipment content of StartUp configuration file
Value
00h
58h
3Fh
3Fh
19h
13h
3Fh
3Bh
00h
73h
08h
ADh
FFh
1Eh
41h
00h
00h
06h
03h
63h
63h
00h
00h
00h
00h
08h
07h
06h
0Ah
02h
00h
00h
Symbol
Page
TxControl
CwConductance
ModConductance
CoderControl
ModWidth
ModWidthSOF
TypeFraming
Page
RxControl1
DecoderControl
BitPhase
RxThreshold
BPSKDemControl
RxControl2
ClockQControl
Page
RxWait
ChannelRedundancy
CRCPresetLSB
CRCPresetMSB
PreSet25
MFOUTSelect
PreSet27
Page
FIFOLevel
TimerClock
TimerControl
TimerReload
IRQPinConfig
PreSet2E
PreSet2F
Rev. 3.4 — 26 January 2010
Description
transmitter pins TX1 and TX2 are switched off, bridge driver
configuration, modulator driven from internal digital circuitry
pulse width for Miller pulse coding is set to standard configuration
bit-collisions always evaluate to HIGH in the data bit stream
MinLevel[3:0] and CollLevel[3:0] are set to maximum
use Q-clock for the receiver, automatic receiver off is switched on,
decoder is driven from internal analog circuitry
automatic Q-clock calibration is switched on
CRC preset value is set using ISO/IEC 14443 A
-
free for user
WaterLevel[5:0] FIFO buffer warning level is set to standard
configuration
TPreScaler[4:0] is set to standard configuration, timer unit restart
function is switched off
Timer is started at the end of transmission, stopped at the beginning
of reception
TReloadValue[7:0]: the timer unit preset value is set to standard
configuration
pin IRQ is set to high-impedance
-
-
free for user
source resistance of TX1 and TX2 is set to minimum
defines the output conductance
ISO/IEC 14443 A coding is set
pulse width of Start Of Frame (SOF)
ISO/IEC 14443 A framing is set
free for user
ISO/IEC 14443 A is set and internal amplifier gain is maximum
BitPhase[7:0] is set to standard configuration
ISO/IEC 14443 A is set
free for user
frame guard time is set to six bit-clocks
channel redundancy is set using ISO/IEC 14443 A
CRC preset value is set using ISO/IEC 14443 A
pin MFOUT is set LOW
056634
ISO/IEC 14443 reader IC
MFRC531
© NXP B.V. 2010. All rights reserved.
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