mfrc531 NXP Semiconductors, mfrc531 Datasheet - Page 104

• Manufacturer Part Number: mfrc531
• Description: Iso/iec 14443 Reader Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
MFRC531_34
Product data sheet
PUBLIC
15.2.3 Digital test signals
15.2.4 Examples of ISO/IEC 14443 A analog and digital test signals
Table 165. Analog test signal selection
Digital test signals can be routed to pin MFOUT by setting bit SignalToMFOUT = logic 1. A
digital test signal is selected using the TestDigiSelect register TestDigiSignalSel[6:0] bits.
The signals selected by the TestDigiSignalSel[6:0] bits are shown in
Table 166. Digital test signal selection
If test signals are not used, the TestDigiSelect register address value must be 00h.
Remark: All other values for TestDigiSignalSel[6:0] are for production test purposes only.
Figure 27
receiving path. RX reference is given to show the Manchester modulated signal on pin
RX.
The signal is demodulated and amplified in the receiver circuitry. Signal VRXAmpQ is the
amplified side-band signal using the Q-clock for demodulation. The signals VCorrDQ and
VCorrNQ were generated in the correlation circuitry. They are processed further in the
evaluation and digitizer circuitry.
Value
B
C
D
E
F
TestDigiSignalSel
[6:0]
F4h
E4h
D4h
C4h
B5h
A5h
96h
83h
E2h
00h
Signal Name
VEvalR
VTemp
reserved
reserved
reserved
shows a MIFARE card’s answer to a request command using the Q-clock
Signal name
s_data
s_valid
s_coll
s_clock
rd_sync
wr_sync
int_clock
BPSK_out
BPSK_sig
no test signal
Rev. 3.4 — 26 January 2010
Description
evaluation signal from the right half-bit
temperature voltage derived from band gap
reserved for future use
reserved for future use
reserved for future use
056634
Description
data received from the card
when logic 1 is returned the s_data and s_coll signals are
valid
when logic 1 is returned a collision has been detected in the
current bit
internal serial clock:
internal synchronized read signal which is derived from the
parallel microprocessor interface
internal synchronized write signal which is derived from the
parallel microprocessor interface
internal 13.56 MHz clock
BPSK output signal
BPSK signal’s amplitude detected
output as defined by the MFOUTSelect register
MFOUTSelect[2:0] bits routed to pin MFOUT
during transmission, this is the encoder clock
during reception this is the receiver clock
…continued
ISO/IEC 14443 reader IC
Table
MFRC531
© NXP B.V. 2010. All rights reserved.
166.
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