uja1079tw/5v0/wd NXP Semiconductors, uja1079tw/5v0/wd Datasheet - Page 15

• Manufacturer Part Number: uja1079tw/5v0/wd
• Description: Lin Core System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 6.
Table 7.
[1]
UJA1079_1
Product data sheet
Bit
0
Bit
15:13
12
11
10
9
8
7
6
5
4
3:0
An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register.
Symbol
WSE2
Symbol
A2, A1, A0 R
RO
V1UI
reserved
LWI
reserved
CI
WI1
POSI
WI2
reserved
Int_Control register
Int_Status register
6.2.6 Int_Status register
Access Power-on
R/W
Access Power-on
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R
[1]
default
0
default
011
0
0
0
0
0
0
0
1
0
0000
Description
WAKE2 sample enable
Description
register address
access status
V1 undervoltage interrupts
LIN wake-up interrupt
cyclic interrupt
wake-up interrupt 1
power-on status interrupt
wake-up interrupt 2
0: sampling continuously
1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled
by WBC)
0: register set to read/write
1: register set to read only
0: no V1 undervoltage warning interrupt pending
1: V1 undervoltage warning interrupt pending
0: no LIN wake-up interrupt pending
1: LIN wake-up interrupt pending
0: no cyclic interrupt pending
1: cyclic interrupt pending
0: no wake-up interrupt 1 pending
1: wake-up interrupt 1 pending
0: no power-on interrupt pending
1: power-on interrupt pending
0: no wake-up interrupt 2 pending
1: wake-up interrupt 2 pending
Rev. 01 — 1 December 2009
LIN core system basis chip
UJA1079
© NXP B.V. 2009. All rights reserved.
15 of 44