peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 66

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

5.1.2.1
Each transmit descriptor consists of 4 consecutive DWORDs located DWORD aligned
in the shared memory. The first 3 DWORDs are written by the host and read by the
corresponding DMA channel using a burst transaction. They provide information about
the next descriptor in the linked list, the attached transmit data buffer, and its size as well
as some control bits.
The fourth DWORD is written by the DMA channel indicating that operation on this
descriptor is finished.
The CPU will write the address of the first descriptor of each linked list to a dedicated
Base Address Register (BTDAi) during initialization procedure. The corresponding DMA
channel start serving the descriptor at these addresses.
Figure 13
Data Sheet
DMAC Transmit Descriptor Lists
Transmit Descriptor List Structure
DWORD1
DWORD2
DWORD3
DWORD4
(DWORD5)
Transmit Descriptor:
Transmit Data Buffer:
31
FE Hold HI
31
0
byte11
byte15
byte19
byte3
byte7
C
Next Transmit Descriptor Pointer
0
Transmit Data Pointer
0
byte10
byte14
byte2
byte6
NO
(dummy)
66
byte1
byte5
byte9
0x0000000
0x0000
byte0
byte4
byte8
DMA Controller and Central FIFOs
0
0
FE Hold HI
written by
CPU
written by
DSCC4
PEB 20534
PEF 20534
2000-05-30