lan9303m Standard Microsystems Corp., lan9303m Datasheet - Page 53

• Manufacturer Part Number: lan9303m
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Dual Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
SMSC LAN9303M/LAN9303Mi
STRAP NAME
LED_en_strap[5:0]
LED_fun_strap[1:0]
auto_mdix_strap_1
manual_mdix_strap_1
autoneg_strap_1
SQE_test_disable_strap_1
Table 4.2 Soft-Strap Configuration Strap Definitions
DESCRIPTION
LED Enable Straps: Configures the default value for the
LED Enable 5-0 (LED_EN[5:0])
Configuration Register
LED Function Straps: Configures the default value for the
LED Function 1-0 (LED_FUN[1:0])
Configuration Register
Port 1 Auto-MDIX Enable Strap: Configures the default
value of the
Hardware Configuration Register
This strap is also used in conjunction with
manual_mdix_strap_1
functionality when the
in the (x=1)
Register (PHY_SPECIAL_CONTROL_STAT_IND_x)
indicates the strap settings should be used for auto-MDIX
configuration.
Note:
Refer to the respective register definition sections for
additional information.
Port 1 Manual MDIX Strap: Configures MDI(0) or MDIX(1)
for Port 1 when the
MDIX Control (AMDIXCTRL)
Special Control/Status Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x)
strap settings are to be used for auto-MDIX configuration.
Note:
Port 1 Auto Negotiation Enable Strap: Configures the
default value of the
of the (x=1)
(PHY_BASIC_CONTROL_x).
This strap also may affect the default value of the following
register bits (x=1):
Refer to the respective register definition sections for
additional information.
Configures the default value of the
1 MII Basic Control Register (P1_MII_BASIC_CONTROL)
when in MII PHY mode. It is not used in internal PHY, RMII
PHY, or MII MAC mode.
Speed Select LSB (PHY_SPEED_SEL_LSB)
Mode (PHY_DUPLEX)
Control Register (PHY_BASIC_CONTROL_x)
10BASE-T Full Duplex
the
(PHY_AN_ADV_x)
PHY Mode (MODE[2:0])
Modes Register (PHY_SPECIAL_MODES_x)
Port x PHY Auto-Negotiation Advertisement Register
Not used in MII PHY, RMII PHY, or MII MAC
mode.
Not used in MII PHY, RMII PHY, or MII MAC
mode.
Port x PHY Special Control/Status Indication
Port x PHY Basic Control Register
AMDIX_EN Strap State Port 1
DATASHEET
auto_mdix_strap_1
Auto-Negotiation (PHY_AN)
Auto-MDIX Control (AMDIXCTRL)
to configure Port 1 Auto-MDIX
(LED_CFG).
(LED_CFG).
53
and
bits of the
bits of the
10BASE-T Half Duplex
bit of the (x=1)
bits of the
(HW_CFG).
SQEOFF
bits of the
Port x PHY Basic
Port x PHY Special
is low and the
LED
bit of the
indicates the
bit of the
Port x PHY
LED
and
enable bit
Duplex
bits of
Auto-
Port
bit
PIN / DEFAULT
VALUE
1b
00b
AMDIX1_LED0P
0b
1b when in internal
PHY mode
(P1_MODE[2:0] =
111b)
else 0b
Revision 1.3 (08-27-09)
Note 4.1