lan9303m Standard Microsystems Corp., lan9303m Datasheet - Page 148

• Manufacturer Part Number: lan9303m
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Dual Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Revision 1.3 (08-27-09)
13.2
0ACh - 19Ch
000h - 04Ch
ADDRESS
068h - 070h
078h - 088h
094h - 098h
OFFSET
05Ch
08Ch
09Ch
0A0h
0A4h
0A8h
050h
054h
058h
060h
064h
074h
090h
The System CSR’s are directly addressable memory mapped registers with a base address offset
range of 050h to 2DCh. These registers are accessed through the I
serial interface. For more information on the various modes and their corresponding address
configurations, see
Table 13.2
reset to their default value on the assertion of a chip-level reset.
The System CSR’s can be divided into 7 sub-categories. Each of these sub-categories contains the
System CSR descriptions of the associated registers. The register descriptions are categorized as
follows:
System Control and Status Registers
Section 13.2.1, "Interrupts," on page 150
Section 13.2.2, "GPIO/LED," on page 154
Section 13.2.3, "EEPROM," on page 158
Section 13.2.4, "Switch Fabric," on page 162
Section 13.2.5, "PHY Management Interface (PMI)," on page 177
Section 13.2.6, "Virtual PHY," on page 179
Section 13.2.7, "Miscellaneous," on page 194
lists the System CSR’s and their corresponding addresses in order. All system CSR’s are
PMI_ACCESS
Table 13.2 System Control and Status Registers
BYTE_TEST
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
FREE_RUN
SYMBOL
PMI_DATA
GPT_CFG
GPT_CNT
Section 2.3, "Modes of Operation," on page
IRQ_CFG
HW_CFG
INT_STS
ID_REV
INT_EN
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
DATASHEET
148
Reserved for Future Use
Chip ID and Revision Register,
Interrupt Configuration Register,
Interrupt Status Register,
Interrupt Enable Register,
Reserved for Future Use
Byte Order Test Register,
Reserved for Future Use
Hardware Configuration Register,
Reserved for Future Use
General Purpose Timer Configuration Register,
Section 13.2.7.4
General Purpose Timer Count Register,
Reserved for Future Use
Free Running Counter Register,
Reserved for Future Use
PHY Management Interface Data Register,
Section 13.2.5.1
PHY Management Interface Access Register,
Section 13.2.5.2
Reserved for Future Use
19.
REGISTER NAME
2
C serial interface or the MIIM/SMI
Section 13.2.1.2
Section 13.2.7.2
Section 13.2.1.3
SMSC LAN9303M/LAN9303Mi
Section 13.2.7.1
Section 13.2.1.1
Section 13.2.7.6
Section 13.2.7.3
Section 13.2.7.5
Datasheet