lan9303m Standard Microsystems Corp., lan9303m Datasheet - Page 124

• Manufacturer Part Number: lan9303m
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Dual Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Revision 1.3 (08-27-09)
8.4.6
8.4.7
Loader is finished, will go into a wait state, and clear the
in the
The data at EEPROM byte 13 and above should be formatted in a sequence of bursts. The first byte
is the total number of bursts. Following this is a series of bursts, each consisting of a starting address,
count, and the count x 4 bytes of data. This results in the following formula for formatting register data:
8-bits number_of_bursts
repeat (number_of_bursts)
Note: The starting address is a DWORD address. Appending two 0 bits will form the register address.
As an example, the following is a 3 burst sequence, with 1, 2, and 3 DWORDs starting at register
addresses 40h, 80h, and C0h respectively:
In order to avoid overwriting the Switch CSR register interface or the PHY Management Interface
(PMI), the EEPROM Loader waits until the
Interface Command Register (SWITCH_CSR_CMD)
Management Interface Access Register (PMI_ACCESS)
write.
The EEPROM Loader checks that the EEPROM address space is not exceeded. If so, it will stop and
set the
Register
of sizes. The address limit is set to the largest value of the specified range.
EEPROM Loader Finished Wait-State
Once finished with the last burst, the EEPROM Loader will go into a wait-state and the
Controller Busy (EPC_BUSY)
Reset Sequence and EEPROM Loader
In order to allow the EEPROM Loader to change the Port 1/2 PHYs and Virtual PHY strap inputs and
maintain consistency with the PHY and Virtual PHY registers, the following sequence is used:
1. After power-up or upon a hardware reset (nRST), the straps are sampled into the device as
2. After the PLL is stable, the main chip reset is released and the EEPROM Loader reads the
A5h, (Burst Sequence Valid Flag)
3h, (number_of_bursts)
16{10h, 1h}, (starting_address1 divided by 4 / count1)
11h, 12h, 13h, 14h, (4 x count1 of data)
16{20h, 2h}, (starting_address2 divided by 4 / count2)
21h, 22h, 23h, 24h, 25h, 26h, 27h, 28h, (4 x count2 of data)
16{30h, 3h}, (starting_address3 divided by 4 / count3)
31h, 32h, 33h, 34h, 35h, 36h, 37h, 38h, 39h, 3Ah, 3Bh, 3Ch (4 x count3 of data)
specified in
EEPROM and configures (overrides) the strap inputs.
16-bits {starting_address[9:2] / count[7:0]}
repeat (count)
EEPROM Command Register
EEPROM Loader Address Overflow (LOADER_OVERFLOW)
(E2P_CMD). The address limit is based on the
8-bits data[31:24], 8-bits data[23:16], 8-bits data[15:8], 8-bits data[7:0]
Section 14.5.2, "Reset and Configuration Strap Timing," on page
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
bit of the
DATASHEET
(E2P_CMD). This can optionally generate an interrupt.
EEPROM Command Register (E2P_CMD)
124
CSR Busy (CSR_BUSY)
and the
eeprom_size_strap
are cleared before performing any register
EEPROM Controller Busy (EPC_BUSY)
MII Busy (MIIBZY)
bit in the
bit of the
SMSC LAN9303M/LAN9303Mi
which specifies a range
EEPROM Command
365.
Switch Fabric CSR
will be cleared.
bit of the
EEPROM
Datasheet
PHY
bit