lan9303m Standard Microsystems Corp., lan9303m Datasheet - Page 127

• Manufacturer Part Number: lan9303m
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Dual Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
SMSC LAN9303M/LAN9303Mi
8.5.3
S
S
A
6
S
A
5
Control Byte
S
A
4
S
A
3
S
S
A
2
I
Following the device addressing, as detailed in
the master continues to send data bytes. Each byte is acknowledged by the device. Following the
fourth byte of the sequence, the master may either send another start condition or halt the sequence
with a stop condition. The internal register address is unchanged following a single write.
Multiple writes are performed when the master sends additional bytes following the fourth
acknowledge. The internal address is automatically incremented and the next register is written. once
the internal address reaches it maximum value, it rolls over to 0. The multiple write is concluded when
the master sends another start condition or stop condition. The internal register address is incremented
for each write including the final. This is not relevant for subsequent writes, since a new register
address would be included on a new write cycle. However, this does affect the internal register address
if it were to be used for reads without first resetting the register address.
For both single and multiple writes, if the master sends an unexpected start or stop condition, the
device will stop immediately and will respond to the next sequence as needed.
The data write to the register occurs after the 32-bits are input. In the event that 32-bits are not written
(master sends a start, or a stop condition occurs unexpectedly), the write is considered invalid and the
register is not affected. Multiple registers may be written in a multiple write cycle, each one being
written after 32-bits. I
Figure 8.10
2
S
A
S
A
6
1
C Slave Write Sequence
S
A
S
A
5
0
Control Byte
S
A
4
0
S
A
3
A
C
K
S
A
2
A
9
illustrates a typical single and multiple register write.
S
A
1
Address Byte
A
8
S
A
A
0
7
A
0
6
A
C
K
A
5
A
9
A
4
2
C writes must not be performed to unused register addresses.
A
8
A
3
Address Byte
A
7
A
2
A
6
A
C
K
Figure 8.10 I
A
D
5
3
1
Data 1 Byte
A
D
4
3
0
.. .
A
3
DATASHEET
Multiple Register Writes
A
2
Single Register Write
C
A
K
D
2
5
D
3
1
D
2
4
2
127
D
A
C
K
3
0
C Slave Writes
Data Byte
.. .
D
2
9
...Data m Byte
D
2
8
Section
S
D
2
7
5
D
D
2
6
4
D
2
5
D
3
D
2
4
D
2
8.5.1, a register is written to the device when
A
C
K
D
1
D
D
2
3
0
Data Byte...
D
A
C
K
2
2
D
D
2
1
3
1
Data m+1 Byte...
D
D
2
0
3
0
.. .
D
2
9
D
2
8
...Data Byte
D
5
D
2
7
D
D
4
2
6
D
D
3
2
5
.. .
D
2
Revision 1.3 (08-27-09)
D
1
...Data n Byte
D
0
D
5
A
C
K
D
4
P
D
3
D
2
D
1
D
0
C
A
K
P