lan9303m Standard Microsystems Corp., lan9303m Datasheet - Page 126

• Manufacturer Part Number: lan9303m
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Dual Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Revision 1.3 (08-27-09)
8.5.2
8.5.2.1
S
S
A
6
S
A
5
Control Byte
S
A
4
S
A
3
S
S
A
2
S
A
6
S
A
1
S
A
5
I
Following the device addressing, as detailed in
the master sends a start condition and control byte with the R/~W bit set. Assuming the slave address
in the control byte matches the device address, the control byte is acknowledged by the device.
Otherwise, the entire sequence is ignored until the next start condition. Following the acknowledge,
the device sends 4 bytes of data. The first 3 bytes are acknowledged by the master and on the fourth,
the master sends a no-acknowledge followed by the stop condition. The no-acknowledge informs the
device not to send the next 4 bytes (as it would in the case of a multiple read). The internal register
address is unchanged following the single read.
Multiple reads are performed when the master sends an acknowledge on the fourth byte. The internal
address is incremented and the next register is shifted out. Once the internal address reaches its
maximum, it rolls over to 0. The multiple read is concluded when the master sends a no-acknowledge
followed by a stop condition. The no-acknowledge informs the device not to send the next 4 bytes.
The internal register address in incremented for each read including the final.
For both single and multiple reads, in the case that the master sends a no-acknowledge on any of the
first three bytes of the register, the device will stop sending subsequent bytes. If the master sends an
unexpected start or stop condition, the device will stop sending immediately and will respond to the
next sequence as needed.
Since data is read serially, register values are latched (registered) at the beginning of each 32-bit read
to prevent the host from reading an intermediate value. The latching occurs multiple times in a multiple
read sequence. In addition, any register that is affected by a read operation (e.g. a clear on read bit)
is not cleared until after all 32-bits are output. In the event that 32-bits are not read (master sends a
no-acknowledge on one of the first three bytes or a start or stop condition occurs unexpectedly), the
read is considered invalid and the register is not affected. Multiple registers may be cleared in a
multiple read cycle, each one being cleared as it is read. I
return all zeros.
Figure 8.9
Control Byte
I
During reset, the I
is complete, the
read, the interface can be considered functional. At this point, the
Hardware Configuration Register (HW_CFG)
is complete. Refer to
S
A
0
2
2
S
A
4
C Slave Read Polling for Reset Complete
C Slave Read Sequence
0
S
A
3
A
C
K
S
A
2
A
9
S
A
1
A
8
Address Byte
S
A
0
A
7
illustrates a typical single and multiple register read.
0
A
6
C
A
K
A
5
A
9
A
4
Byte Order Test Register (BYTE_TEST)
Address Byte
A
8
A
3
2
A
7
C slave interface will not return valid data. To determine when the reset condition
A
2
A
6
A
C
K
Section 4.2, "Resets," on page 48
A
5
S
A
4
S
A
6
A
3
S
A
5
Control Byte
A
2
Figure 8.9 I
S
A
4
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
A
C
K
S
A
3
S
S
A
2
S
A
6
DATASHEET
S
A
1
S
A
5
Multiple Register Reads
Control Byte
Single Register Read
S
A
0
R/~W
S
A
4
1
S
A
3
A
C
K
2
126
S
A
2
C Slave Reads
D
3
1
Data 1 Byte
S
A
1
D
3
0
can be polled to determine when the device initialization
S
A
0
.. .
R/~W
Section
1
A
C
K
D
2
5
D
3
1
D
2
4
D
3
0
A
C
K
Data Byte
D
2
9
8.5.1, a register is read from the device when
.. .
...Data m Byte
for additional information.
should be polled. Once the correct pattern is
D
2
8
2
S
2
7
D
4
C reads from unused register addresses
D
2
6
D
3
D
2
5
D
2
D
2
4
D
1
A
C
K
Device Ready (READY)
D
0
D
2
3
Data Byte...
A
C
K
D
2
2
D
3
1
Data m+1 Byte... ...Data n Byte
D
2
1
D
3
0
SMSC LAN9303M/LAN9303Mi
D
2
0
D
2
9
.. .
D
2
8
...Data Byte
D
2
7
D
5
D
2
6
D
4
.. .
D
3
D
2
D
1
D
4
D
D
0
3
Datasheet
A
C
K
D
2
bit in the
P
D
1
D
0
A
C
K
P