isp1760 NXP Semiconductors, isp1760 Datasheet - Page 18

• Manufacturer Part Number: isp1760
• Description: Hi-speed Universal Serial Bus Host Controller For Embedded Applications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13257
Product data sheet
7.3.3 PIO mode access—register read cycle
7.3.4 PIO mode access—register write cycle
7.3.5 DMA—read and write operations
The PIO register read access is similar to a general register access. It is not necessary to
set a prefetching address before a register read.
The ISP1760 register read address will not be automatically incremented during
consecutive read accesses, unlike in a series of ISP1760 memory read cycles. The
ISP1760 register read address must be correctly specified before every access.
The PIO register write access is similar to a general register access. It is not necessary to
set a prefetching address before a register write.
The ISP1760 register write address will not be automatically incremented during
consecutive write accesses, unlike in a series of ISP1760 memory read cycles. The
ISP1760 register write address must be correctly specified before every access.
The internal ISP1760 Host Controller DMA is a slave DMA. The host system processor or
DMA must ensure the data transfer to or from the ISP1760 memory.
The ISP1760 DMA supports a DMA burst length of 1, 4, 8 and 16 cycles for both the 16-bit
and 32-bit data bus width. DREQ will be asserted at the beginning of the first burst of a
DMA transfer and will be deasserted on the last cycle (RD_N or WR_N active pulse) of
that burst. It will be reasserted shortly after the DACK deassertion, as long as the DMA
transfer counter was not reached. DREQ will be deasserted on the last cycle when the
DMA transfer counter is reached and will not reasserted until the DMA reprogramming is
performed. Both the DREQ and DACK signals are programmable as active LOW or active
HIGH, according to the system requirements.
The DMA start address must be initialized in the respective register, and the subsequent
transfers will automatically increment the internal ISP1760 memory address. A register or
memory access or access to other system memory can occur in between DMA bursts,
whenever the bus is released because DACK is deasserted, without affecting the DMA
transfer counter or the current address.
Any memory area can be accessed by the system’s DMA at any starting address because
there are no predefined memory blocks. The DMA transfer must start on a word or Double
Word address, depending on whether the data bus width is set to 16 bit or 32 bit. DMA is
the most efficient method to initialize the payload area, to reduce the CPU usage and
overall system loading.
The ISP1760 does not implement EOT to signal the end of a DMA transfer. If
programmed, an interrupt may be generated by the ISP1760 at the end of the DMA
transfer.
The slave DMA of the ISP1760 will issue a DREQ to the DMA controller of the system to
indicate that it is programmed for transfer and data is ready. The system DMA controller
may also start a transfer without the need of the DREQ, if the ISP1760 memory is
available for the data transfer and the ISP1760 DMA programming is completed.
Rev. 01 — 8 November 2004
Embedded Hi-Speed USB host controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1760
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