isp1761 NXP Semiconductors, isp1761 Datasheet - Page 18

• Manufacturer Part Number: isp1761
• Description: Hi-speed Universal Serial Bus On-the-go Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1761_4
Product data sheet
The RAM is structured in blocks of PTDs and payloads so that while the USB is executing
on an active transfer-based PTD, the processor can simultaneously fill up another block
area in the RAM. A PTD and its payload can then be updated on-the-fly without stopping
or delaying any other USB transaction or corrupting the RAM data.
Some of the design features are:
Table 4.
Memory map
ISO
INT
ATL
Payload
•
•
•
•
The address range of the internal RAM buffer is from 0400h to FFFFh.
The internal memory contains isochronous, interrupt and asynchronous PTDs, and
respective defined payloads.
All accesses to the internal memory are double-word aligned.
Internal memory address range calculation:
Memory address = (CPU address
Memory address
Rev. 04 — 5 March 2007
CPU address
0400h to 07FFh
0800h to 0BFFh
0C00h to 0FFFh
1000h to FFFFh
0400h) (shift right >> 3). Base address is 0400h.
Hi-Speed USB OTG controller
Memory address
0000h to 007Fh
0080h to 00FFh
0100h to 017Fh
0180h to 1FFFh
© NXP B.V. 2007. All rights reserved.
ISP1761
18 of 163