isp1761 NXP Semiconductors, isp1761 Datasheet - Page 120

• Manufacturer Part Number: isp1761
• Description: Hi-speed Universal Serial Bus On-the-go Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 133. DMA Interrupt Reason register (address 0250h) bit allocation
[1]
ISP1761_4
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
10.7.5 DMA Interrupt Reason register
R/W
R/W
15
0
0
7
0
0
Table 132. DMA Hardware register (address 023Ch) bit description
This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a
DMA command is executed. An interrupt source is cleared by writing logic 1 to the
corresponding bit. On detecting the interrupt, the external microprocessor must read the
DMA Interrupt Reason register and mask it with the corresponding bits in the DMA
Interrupt Enable register to determine the source of the interrupt.
The bit allocation is given in
Table 134. DMA Interrupt Reason register (address 0250h) bit description
Bit
7 to 4
3
2
1 to 0
Bit
15 to 13
12
11
10
reserved
R/W
R/W
14
0
0
6
0
0
Symbol
-
DACK_POL
DREQ_POL
-
Symbol
-
GDMA_STOP
-
INT_EOT
R/W
R/W
13
0
0
5
0
0
Description
reserved
DACK Polarity: Selects the DMA acknowledgment polarity.
0 — DACK is active LOW
1 — DACK is active HIGH
DREQ Polarity: Selects the DMA request polarity.
0 — DREQ is active LOW
1 — DREQ is active HIGH
reserved
Rev. 04 — 5 March 2007
Description
reserved
GDMA Stop: When the GDMA_STOP command is issued to DMA
Command registers, it means that the DMA transfer has
successfully terminated.
reserved
Internal EOT: Logic 1 indicates that an internal EOT is detected;
see
Table
GDMA_
STOP
R/W
R/W
Table
12
0
0
4
0
0
133.
reserved
135.
reserved
[1]
R/W
R/W
11
0
0
3
0
0
INT_EOT
R/W
R/W
10
0
0
2
0
0
Hi-Speed USB OTG controller
reserved
R/W
R/W
9
0
0
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1761
[1]
XFER_OK
DMA_
120 of 163
R/W
R/W
8
0
0
0
0
0