isp1705 NXP Semiconductors, isp1705 Datasheet - Page 63

• Manufacturer Part Number: isp1705
• Description: Ulpi Hi-speed Usb Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 49.
ISP1705_1
Product data sheet
Bit
Symbol
Reset
Access
PWR_CTRL - Power control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation
11.15 PWR_CTRL register
R/W/S/C
7
0
This vendor-specific register controls the power feature of the ISP1705. The bit allocation
of the register is given in
Table 50.
Bit
7 to 5
4
3
2
1 to 0
reserved
R/W/S/C
6
0
Symbol
-
DP_WKPU_EN
BVALID_FALL
BVALID_RISE
-
PWR_CTRL - Power control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,
C = 3Fh) bit description
R/W/S/C
5
0
Rev. 01 — 13 June 2008
Table
Description
reserved; the link must never write logic 1 to these bits
DP weak pull-up enable: Enable the weak pull-up resistor on the DP
pin (R
V
mode, the DP weak pull-up will be enabled, regardless of the value of
this register bit.
0 — DP weak pull-up is disabled.
1 — DP weak pull-up is enabled when V
BVALID fall: Enables RXCMDs for HIGH-to-LOW transitions on
BVALID. When BVALID changes from HIGH to LOW, the ISP1705
will send an RXCMD to the link with the ALT_INT bit set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
BVALID rise: Enables RXCMDs for LOW-to-HIGH transitions on
BVALID. When BVALID changes from LOW to HIGH, the ISP1705
will send an RXCMD to the link with the ALT_INT bit set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
reserved; the link must never write logic 1 to these bits
DP_WKPU_
A_SESS_VLD
R/W/S/C
49.
EN
weakUP(DP)
4
0
threshold. Note that when the ISP1705 is in UART
) in synchronous mode when V
BVALID_
R/W/S/C
FALL
3
0
BVALID_
R/W/S/C
RISE
ULPI Hi-Speed USB transceiver
2
0
BUS
> V
R/W/S/C
BUS
A_SESS_VLD
1
0
© NXP B.V. 2008. All rights reserved.
ISP1705
is above the
reserved
R/W/S/C
.
0
0
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