isp1705 NXP Semiconductors, isp1705 Datasheet - Page 15

• Manufacturer Part Number: isp1705
• Description: Ulpi Hi-speed Usb Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1705_1
Product data sheet
Fig 6.
CHIP_SEL_N
DATA[7:0]
REG1V8
V
Internal
CLOCK
(output)
CC(I/O)
XTAL1
POR
t1 = V
t2 = V
non-active.
t3 = Chip select turns from non-active to active. The ISP1705 regulator starts to turn on. ULPI pads are not in 3-state and may
drive to either LOW or HIGH. It is recommended that the link ignores ULPI pins status during t
t4 = Power-on reset threshold is reached and the POR pulse is generated. After the POR pulse, ULPI pins are driven to a
defined level. DIR is driven to HIGH and the other pins are driven to LOW.
t5 = The PLL is stabilized after t
from HIGH to LOW. The link must drive DATA[7:0] and STP to LOW as the idle state. The link will then issue a reset command
to initialize the ISP1705.
t6 = The power-up sequence is completed and the ULPI bus interface is ready for use.
Power-up and reset sequence required before the ULPI bus is ready for use
V
NXT
STP
DIR
CC
t1
CC
CC(I/O)
is applied to the ISP1705.
t2
is turned on. ULPI interface pins CLOCK, DATA[7:0], DIR and NXT are in 3-state as long as chip select is
t3
t
PWRUP
t4
d(det)clk(osc)
t
d(det)clk(osc)
+ t
startup(PLL)
Rev. 01 — 13 June 2008
+ t
startup(PLL)
. The CLOCK pin starts to output 60 MHz. The DIR pin will transition
t5
internal clocks stable
RESET command
TXCMD
D
ULPI Hi-Speed USB transceiver
internal reset
PWRUP
.
© NXP B.V. 2008. All rights reserved.
ISP1705
RXCMD
update
004aaa987
bus idle
t6
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