isp1705 NXP Semiconductors, isp1705 Datasheet
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isp1705 Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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... It allows USB Application-Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs) or any system chip set to interface with the physical layer of the USB through an 8-pin (DDR) or 12-pin (SDR) interface. The ISP1705 can interface to devices with digital I/O voltages in the range of 3 3.6 V. The ISP1705 is available in HVQFN36 and TFBGA36 packages. ...
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... IEC 61000-4 contact on the DP and DM pins ISP1705_1 Product data sheet pulsing session request methods BUS voltage comparators BUS suspend mode and 0 Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver power switch BUS is not present CC(I/O) © NXP B.V. 2008. All rights reserved ...
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... Marking Table 2. Type number ISP1705HN ISP1705AET [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1705_1 Product data sheet Ordering information Name Description HVQFN36 plastic thermal enhanced very thin quad flat package; no leads; 36 terminals; body 5 TFBGA36 plastic thin fi ...
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... SELECTION PLL CRYSTAL OSCILLATOR interface voltage internal power POWER-ON POR RESET V REF VOLTAGE REGULATOR 15 11 GND n.c. Table 3. Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver 6 DP HI-SPEED USB ATX TERMINATION 5 DM RESISTORS OTG MODULE DETECTOR V BUS COMPARATORS 13 V SRP CHARGE ...
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... Pin configuration TFBGA36 Rev. 01 — 13 June 2008 ULPI Hi-Speed USB transceiver 27 DATA5 26 V CC(I/O) 25 DATA6 24 DATA7 ISP1705HN 23 NXT 22 STP 21 V CC(I/O) 20 RESET_N 19 DIR 004aaa995 ISP1705AET 004aab094 Transparent top view ISP1705 © NXP B.V. 2008. All rights reserved ...
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... V to 4.5 V Remark: Below 3.0 V, USB full-speed and low-speed transactions are not guaranteed to work, though some devices may work with the ISP1705 at these voltages. I identification (ID) pin of the micro-USB connector; if this pin is not in use, connect it directly to the REG3V3 pin (an internal 400 k pull-up resistor is present on this pin) plain input ...
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... P input I/O supply voltage 0.1 F decoupling capacitor is recommended I active-LOW chip select input; when this pin is not in use, connect it to GND plain input Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver Table 6 Table 6 © NXP B.V. 2008. All rights reserved ...
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... Type Description I active-HIGH chip select input; when this pin is not in use, connect CC(I/O) plain input I/O ULPI data pin 2 3-state output; plain input P ground Section 8.12. Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 8. Functional description 8.1 ULPI interface controller The ISP1705 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . This interface must be connected to a USB link. The ULPI interface controller provides the following functions: • ULPI-compliant interface and register set • ...
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... Other internal frequencies for data conversion and data recovery 8.6 UART buffer The UART buffer includes circuits to support the transparent UART signaling between the DATA0 or DATA1 pin and the pin. When the ISP1705 is put into UART mode, it acts as a voltage level shifter between the following pins: • From DATA0 (V • ...
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... ID pin that is different from the previously reported state, an RXCMD status update will be sent to the USB link interrupt will be asserted. • If the micro-B end of the cable is plugged in (or nothing is plugged in), the ISP1705 will report that ID_GND is logic 1. The USB link must be in the B-device state. • ...
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... Port power control For an OTG or host application, the ISP1705 uses the PSW_N pin to control the external power switch for the V power switch can be connected to the FAULT pin of the ISP1705 to indicate to the ULPI link the V When the FAULT pin is not used, connect it to GND. ...
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... LOW. Before beginning USB packets, the link must set the RESET bit in the FUNC_CTRL register (see the RESET bit is set, the ISP1705 will assert DIR until the internal reset completes. The ISP1705 will automatically deassert DIR and clear the RESET bit when the reset has completed ...
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... CC(I/O) non-active Chip select turns from non-active to active. The ISP1705 regulator starts to turn on. ULPI pads are not in 3-state and may drive to either LOW or HIGH recommended that the link ignores ULPI pins status during Power-on reset threshold is reached and the POR pulse is generated. After the POR pulse, ULPI pins are driven to a defi ...
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... NXP Semiconductors 8.11.1 Interface protection By default, the ISP1705 enables a weak pull-up resistor on STP. If the STP pin is unexpectedly HIGH at any time, the ISP1705 will protect the ULPI interface by enabling weak pull-down resistors on DATA[7:0]. The interface protect feature prevents unwanted activity of the ISP1705 whenever the ULPI interface is not correctly driven by the link ...
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... NXT • STP • RESET_N ISP1705_1 Product data sheet t PWRDN Hi-Z (ignored) Hi-Z Hi-Z (ignored) Hi-Z Section 8.11.1. Section 9.2. pin. V powers the on-chip pads of the following pins: CC(I/O) CC(I/O) Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver Hi-Z (ignored) 004aaa988 © NXP B.V. 2008. All rights reserved ...
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... The ISP1705 provides an internal pull-up resistor (R The pull-up resistor must first be enabled by setting the ID_PULLUP register bit to logic 1. If the state of ID has changed, the ISP1705 will send an RXCMD or interrupt to the link. If the link does not receive any RXCMD or interrupt by time t changed ...
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... Recommended V capacitor value BUS V BUS 6 120 Rev. 01 — 13 June 2008 ULPI Hi-Speed USB transceiver 10.3.3. Figure 9. Table 4 provides the recommended capacitor capacitor (C ) VBUS ISP1705 © NXP B.V. 2008. All rights reserved ...
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... Allowed crystal or clock frequency on the XTAL1 pin LOW 19.2 MHz HIGH 26 MHz LOW 24 MHz HIGH 13 MHz Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver REG3V3 ISP1705 V BUS R I(idle)(VBUS) 004aab045 . When in use, an external pull-up BUS Section 11.7) to logic 1. . BUS © NXP B.V. 2008. All rights reserved ...
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... NXT ULPI next data output pin. Synchronous to the rising edge of CLOCK. The ISP1705 holds NXT at LOW, by default. When DIR is LOW and the link is sending data to the ISP1705, NXT will be asserted to notify the link to provide the next data byte. When DIR is HIGH ...
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... NXP Semiconductors and the ISP1705 is sending data to the link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not used for register read data or the RXCMD status update. This pin can be 3-stated when chip select is deasserted. ...
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... When V ISP1705, the application system must detect the low voltage condition and set chip select to deassert (that is, put the ISP1705 in Power-down mode). This is to protect the ULPI and USB interfaces from driving wrong levels. Under this condition, the V leak to USB pins (V Section must be driven to a defi ...
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... NXP Semiconductors When the ISP1705 is put into Power-down mode by disabling chip select, all the digital pins (see inputs. These pins must be driven to defined states or terminated by using pull-up or pull-down resistors to avoid a floating input condition. Other pins (see not powered. In this mode, minimum current will be drawn by V select status ...
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... DIR is always asserted during low-power, serial and UART modes. Stop: In synchronous mode, the link drives STP to HIGH for one cycle after the last byte of data is sent to the ISP1705. The link can optionally assert STP to force DIR to be deasserted. In low-power, serial and UART modes, the link holds STP at HIGH to wake up the ISP1705, causing the ULPI bus to return to synchronous mode ...
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... If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1705 to 6-pin serial mode. In 6-pin serial mode, the data bus definition changes to that shown in 6PIN_FSLS_SERIAL bit in the INTF_CTRL register (see 6-pin serial mode, the link asserts the STP signal ...
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... SE0 INT Reserved [ input output. 9.2.5 Transparent UART mode In transparent UART mode, the ISP1705 functions as a voltage level shifter between following pins: • From pin DATA0 (V • From pin DP (2.7 V level) to pin DATA1 (V The USB transceiver is used to drive the UART transmitting signal on the DM line. The rise time and the fall time of the transmitting signal is determined by whether a full-speed or low-speed transceiver is in use ...
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... UART mode is enabled. 2. The 39 3. One clock cycle after DIR goes from LOW to HIGH, the ISP1705 will drive the data bus for five clock cycles. This is to charge the DATA0 pin to a HIGH level for a slow link ...
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... TXCMD DATA (REGW) (1) (2) UART mode signals DIR STP NXT UART mode Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver turnaround 0001 0001 UART mode signals turnaround synchronous 0000 0000 mode signals © NXP B.V. 2008. All rights reserved. 004aaa865 004aaa867 ...
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... A Hi-Speed USB peripheral, host or OTG device handles more than one electrical state as defined in Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 . The ISP1705 accommodates various states through register settings of the XCVRSELECT[1:0], TERMSELECT, OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN bits. ...
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... DM_ RPU_ RPD_ RPD_ PULL DP_EN DP_EN DM_EN DOWN ISP1705 HSTERM_ © NXP B.V. 2008. All rights reserved ...
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... TXCMD By default, the link must drive the ULPI bus to its idle state of 00h. To send commands and USB packets, the link drives a nonzero value on DATA[7:0] to the ISP1705 by sending a byte called TXCMD. Commands include USB packet transmissions, and register reads and writes. Once the TXCMD is interpreted and accepted by the ISP1705, the NXT signal is asserted and the link can follow up with the required number of data bytes ...
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... NXP Semiconductors The ISP1705 will automatically send an RXCMD whenever there is a change in any of the RXCMD data fields. The link must be able to accept an RXCMD at any time; including single RXCMDs, back-to-back RXCMDs, and RXCMDs at any time during USB receive packets when NXT is LOW. An example is shown in refer to UTMI+ Low Pin Interface (ULPI) Specifi ...
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... HS_Differential_Receiver_Output. 10.3.2 V state encoding BUS USB devices must monitor the V starting a session and SRP. The V voltage level on V The SESS_END and SESS_VLD indicators in the V internal comparators built-in to the ISP1705, and encoded as shown in Table 20. Table 20. Value ...
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... external circuit must be used to detect overcurrent conditions. If the external overcurrent detector provides a digital fault signal, then the fault signal must be connected to the ISP1705 FAULT input pin, and the link must do the following: 1. Set the IND_COMPL bit in the INTF_CTRL register (see logic 1, depending on the polarity of the external fault signal ...
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... An RxActive event can be communicated using two methods. The first method is for the ISP1705 to simultaneously assert DIR and NXT. The second method is for the ISP1705 to send an RXCMD to the link with the RxActive field in the RxEvent bits set to logic 1. The link must be capable of detecting both methods. RxActive frames the receive packet from the fi ...
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... NXP Semiconductors 10.3.4.2 RxError When the ISP1705 has detected an error while receiving a USB packet, it deasserts NXT and sends an RXCMD with the RxError field set to logic 1. The received packet is no longer valid and must be dropped by the link. 10.3.4.3 HostDisconnect HostDisconnect is encoded into the RxEvent field of the RXCMD. HostDisconnect is valid only when the ISP1705 is confi ...
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... OPMODE[1:0] to 00b and begins sending USB packets. For more information, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . ISP1705_1 Product data sheet 19. Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver Section 11.5) and setting © NXP B.V. 2008. All rights reserved ...
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... K (10b) (00b) TXCMD NOPID K K ... (HS) 10 (chirp) squelch peripheral chirp K (10b) (00b) Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver host chirp TXCMD (REGW) NOPID K J ... K J host chirp K (10b) or chirp J (01b) RXCMDs TXCMD (REGW ...
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... CLOCK DATA [ 7:0 ] TXCMD DIR STP NXT Fig 16. Example of using the ISP1705 to transmit and receive USB data 10.6.1 USB packet timing 10.6.1.1 ISP1705 pipeline delays The ISP1705 delays (in clock cycles) are shown in to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.2.6.2 . Table 23. ...
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... Any subsequent transmission can occur after this time. USB interpacket delay (88 to 192 high-speed bit times) EOP link decision time ( clocks) Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver IDLE TXCMD TX start delay (one to two clocks) © ...
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... PRE PID and the first bit of the low-speed packet SYNC. The ISP1705 will drive a J for at least one full-speed bit time after sending the PRE PID, after which the pull-up resistor can hold the J state on the bus ...
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... LINESTATE, and asserts STP to wake up the PHY. 4. EOP: When STP is asserted, the ISP1705 on the host side automatically appends an EOP of two bits of SE0 at low-speed bit rate, followed by one bit of J. The ISP1705 on the host side knows to add the EOP because DP_PULLDOWN and DM_PULLDOWN are set to 1b for a host ...
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... Rev. 01 — 13 June 2008 ULPI Hi-Speed USB transceiver EOP resume K K ... K TXCMD K 10b K SE0 J SE0 J 10b K SE0 Figure 21 timing is not to scale, and does not ISP1705 idle 00b 00b J 004aab123 © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors The sequence of events related to a host and a peripheral, both with ISP1705 follows: 1. High speed idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and ...
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... Product data sheet FS suspend TXCMD TXCMD (REGW) NOPID 01b 00b FS J (01b) LINESTATE K LINESTATE J 01b 00b FS J (01b) Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver resume K HS idle TXCMD ... (REGW) 00b 10b 00b FS K (10b) SQUELCH (00b) TXCMD ...
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... Depending on the original speed, the link follows one of the protocols detailed here. In Figure 22, timing is not to scale, and not all RXCMD LINESTATE updates are shown. The sequence of events related to a host and a peripheral, both with ISP1705 follows: 1. Both the host and the peripheral are assumed low-power mode. ...
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... SYNC and EOP bytes in the data payload when transmitting packets. The ISP1705 will not automatically generate SYNC and EOP patterns when OPMODE[1:0] is set to 11b. The ISP1705 will still NRZI encode data and perform bit stuffing. An example of a sequence is shown in packets using the TXCMD (NOPID) type. The ISP1705 does not provide a mechanism to control bit stuffi ...
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... NXP Semiconductors PHY will not transmit any EOP. The ISP1705 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the link must set OPMODE to 10b. CLOCK TXCMD ...
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... ID detection The ISP1705 provides an internal pull-up resistor to sense the state of the ID pin. The pull-up resistor must first be enabled by setting the ID_PULLUP register bit to logic 1. If the state of pin ID has changed, the ISP1705 will send an RXCMD or interrupt to the link by time t not changed. ...
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... Fig 25. Example of transmit followed by receive in 3-pin serial mode ISP1705_1 Product data sheet TRANSMIT DATA EOP TRANSMIT DATA SYNC EOP Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver RECEIVE SYNC DATA EOP 004aaa692 RECEIVE DATA EOP 004aaa693 © NXP B.V. 2008. All rights reserved. ...
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... The ISP1705 will not immediately enable its output buffers, but will delay the enabling of its buffers until the next clock edge, avoiding bus contention. When the data transfer is no longer required by the ISP1705, it changes DIR from HIGH to LOW and starts to immediately turn off its output drivers. The link senses the change of DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle, avoiding data bus contention ...
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... Section 11.14 on page 3Eh 3Fh Section 11.15 on page 62 Description Vendor ID low: Lower byte of the NXP vendor ID supplied by USB-IF; fixed value of CCh Description Vendor ID high: Upper byte of the NXP vendor ID supplied by USB-IF; fixed value of 04h © NXP B.V. 2008. All rights reserved. ISP1705 ...
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... ULPI Hi-Speed USB transceiver Table 28. Description Product ID low: Lower byte of the NXP product ID number; fixed value of 05h Table 29. Description Product ID high: Upper byte of the NXP product ID number; fixed value of 17h TERM XCVRSELECT[1:0] SELECT R/W/S/C R/W/S/C R/W/S/C © NXP B.V. 2008. All rights reserved. ISP1705 0 1 R/W/S ...
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... Enable the full-speed transceiver 10b — Enable the low-speed transceiver 11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is automatically prefixed) Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver © NXP B.V. 2008. All rights reserved ...
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... The complement output signal is not qualified with the internal A_VBUS_VLD comparator Indicator complement: Informs the PHY to invert the FAULT input signal, generating the complement output. 0b — The ISP1705 will not invert the FAULT signal 1b — The ISP1705 will invert the FAULT signal reserved Clock suspend: Active-LOW clock suspend. ...
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... Table 33. Bit Symbol 2 CARKIT_MODE 1 3PIN_FSLS_SERIAL 0 6PIN_FSLS_SERIAL 11.7 OTG_CTRL register This register controls various OTG functions of the ISP1705. The bit allocation of the OTG_CTRL register is given in Table 34. OTG_CTRL - OTG control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit allocation Bit 7 Symbol USE_EXT_ DRV_ VBUS_IND ...
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... ULPI Hi-Speed USB transceiver indicator: Informs the PHY to use an external valid indicator signal input from the BUS through a resistor. Used for the V BUS is discharged (see BUS BUS through a resistor. If the link sets BUS BUS BUS © NXP B.V. 2008. All rights reserved. ISP1705 BUS ...
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... ID_GND_F R/W/S/C R/W/S/C Rev. 01 — 13 June 2008 ULPI Hi-Speed USB transceiver SESS_ SESS_ VBUS_ END_R VALID_R VALID_R R/W/S/C R/W/S/C R/W/S SESS_ SESS_ VBUS_ END_F VALID_F VALID_F R/W/S/C R/W/S/C R/W/S/C © NXP B.V. 2008. All rights reserved. ISP1705 0 HOST_ DISCON_R 1 R/W/S/C 0 HOST_ DISCON_F 1 R/W/S ...
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... USB_INTR_L register The bits of the USB_INTR_L register are automatically set by the ISP1705 when an unmasked change occurs on the corresponding interrupt source signal. The ISP1705 will automatically clear all bits when the link reads this register, or when the PHY enters low-power mode. ...
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... Rev. 01 — 13 June 2008 ULPI Hi-Speed USB transceiver SESS_ SESS_ VBUS_ END_L VALID_L VALID_L Table 44. This register indicates the LINE STATE1 © NXP B.V. 2008. All rights reserved. ISP1705 0 HOST_ DISCON_L LINE STATE0 ...
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... Scratch: This is an empty register byte for testing purposes. Software can read, write, set and clear this register. The functionality of the PHY will not be affected. Section 11.6) is set. When entering RXD_EN TXD_EN R/W/S/C R/W/S/C R/W/S/C © NXP B.V. 2008. All rights reserved. ISP1705 0 reserved 0 R/W/S ...
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... NXP Semiconductors 11.15 PWR_CTRL register This vendor-specific register controls the power feature of the ISP1705. The bit allocation of the register is given in Table 49. PWR_CTRL - Power control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit allocation Bit 7 Symbol reserved Reset 0 Access R/W/S/C R/W/S/C Table 50. Bit ...
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... The ISP1705 has been tested according to the additional requirements listed in Universal Serial Bus Specification Rev. 2.0, Section 7.1.1 . The short circuit withstand test and the AC stress test were performed for 24 hours, and the ISP1705 was found to be fully operational after the test completed. ...
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... OL Rev. 01 — 13 June 2008 ULPI Hi-Speed USB transceiver Min Typ 0. 0 25.65 - 55. 240 - 750 - 600 - - [ Min Typ 0.7V - CC(I/ 0.4 - CC(I/O) ISP1705 Max Unit 1 100 A 330 Max Unit - V 0.3V V CC(I/ © NXP B.V. 2008. All rights reserved ...
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... may increase because of the cross current +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. CC(I/O) amb Conditions Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver Min Typ Max - - 0 ...
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... ULPI Hi-Speed USB transceiver Min Typ 0 2 1 2.8 - 1.3 - 3.0 - 1425 1500 100 125 100 - 525 - 300 - 360 - 700 - 900 - 1 © NXP B.V. 2008. All rights reserved. ISP1705 Max Unit 2 0.3 V 3.6 V 2.0 V 3.6 V 1575 150 k 150 mV 625 +500 mV +10 mV +10 mV 440 mV 1100 mV 500 mV +1 ...
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... A-device and B-device for A-device and B-device connect to REG3V3 when BUS CHRG_VBUS = 1 connect to GND when BUS DISCHRG_VBUS = 1 not in Power-down mode BUS chip deasserted (Power-down mode) V lost (Power-down CC(I/O) mode) Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver Min Typ Max Unit 14.25 15 15.75 k 14.25 15 15.75 k 40.5 45 49.5 40 ...
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... Conditions = +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. CC(I/O) amb Conditions in UART mode = +85 C; unless otherwise specified. amb Conditions Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver Min Typ Max Unit - - 0 ...
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... Table 6 see Table 6 only for square wave input only for square wave input = +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. CC(I/O) amb Conditions Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver Min Typ Max 0 ...
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... DIR output-only pin NXT bidirectional pins (DATA[3:0]) as output pins DATA[3:0], CLOCK, DIR, NXT, STP 4 Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver Figure 30. Min Typ Max Unit 6 6 ...
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... 185 pF 185 pF 185 pF; DATA0 185 pF; DATA0 DATA1 DP to DATA1 DP to DATA1 DP to DATA1 Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver Min Typ Max 500 - - 500 - - ...
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... Figure Figure 0 PLH(drv) differential V CRS data lines 2 CRS 0 PLH(rcv) t PLH(se 0 RX_DM ISP1705 Max Unit 0 PHL(drv) V CRS 004aaa573 V CRS t PHL(rcv) t PHL(se) 0.9 V 001aai187 © NXP B.V. 2008. All rights reserved. ...
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... ESR capacitor 6.5 F use low ESR capacitor IP4359CX4/LF; Wafer-Level Chip-Scale Package (WLCSP); ESD IEC 61000-4-2 level contact air discharge compliant protection. Note: ISP1705 and IP4359CX4/LF together have an IEC 61000-4-2 contact discharge tolerance supply 19 ...
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... USB STANDARD-B GND RECEPTACLE 4 C VBUS SHIELD 5 SHIELD 6 This figure shows the HVQFN pinout. For the TFBGA ballout, see (1) Connect to either GND depending on the clock frequency used. See CC(I/O) Fig 31. ISP1705 in peripheral-only application CC(I/O) C bypass CC(I/ bypass C bypass ...
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... RECEPTACLE C VBUS A1 SHIELD 6 IP4359CX4/LF SHIELD 7 B1 SHIELD 8 SHIELD 9 This figure shows the HVQFN pinout. For the TFBGA ballout, see (1) Connect to either GND depending on the crystal frequency used. See CC(I/O) Fig 32. ISP1705 in OTG application CC(I/O) C bypass CC(I/ bypass V CC(I/O) 21 ...
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... STANDARD-A RECEPTACLE GND C VBUS 4 SHIELD 5 SHIELD 6 C bypass This figure shows the HVQFN pinout. For the TFBGA ballout, see (1) Connect to either GND depending on the crystal frequency used. See CC(I/O) Fig 33. ISP1705 in host application CC(I/O) C bypass CHIP_SEL CC(I/ bypass ...
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... 5.1 3.75 5.1 3.75 0.4 3.2 4.9 3.45 4.9 3.45 REFERENCES JEDEC JEITA - - - MO-220 Rev. 01 — 13 June 2008 ULPI Hi-Speed USB transceiver detail 2 scale 0.5 3.2 0.1 0.05 0.05 0.1 0.3 EUROPEAN PROJECTION ISP1705 SOT818 ISSUE DATE 03-06-13 © NXP B.V. 2008. All rights reserved ...
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... 3.6 3.6 0.5 2.5 2.5 0.15 3.4 3.4 REFERENCES JEDEC JEITA - - - - - - Rev. 01 — 13 June 2008 ULPI Hi-Speed USB transceiver detail 0.05 0.08 0.1 EUROPEAN PROJECTION ISP1705 SOT912-1 y ISSUE DATE 05-08-09 05-09-01 © NXP B.V. 2008. All rights reserved ...
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... Solder bath specifications, including temperature and impurities ISP1705_1 Product data sheet Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver © NXP B.V. 2008. All rights reserved ...
Page 81
... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 36. Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver Figure 36) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...
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... Effective Series Resistance Field Programmable Gate-Array Full Speed Human Body Model Host Negotiation Protocol High Speed Identification International Electrotechnical Commission Low Speed Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver peak temperature time 001aac844 © NXP B.V. 2008. All rights reserved ...
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... Universal Asynchronous Receiver-Transmitter UTMI+ Low Pin Interface Universal Serial Bus USB Implementers Forum USB Transceiver Macrocell Interface USB Transceiver Macrocell Interface Plus Wafer-Level Chip-Scale Package Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver © NXP B.V. 2008. All rights reserved ...
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... Electrostatic discharge immunity test (IEC 61000-4-2) 22. Revision history Table 76. Revision history Document ID Release date ISP1705_1 20080613 ISP1705_1 Product data sheet Data sheet status Change notice Product data sheet - Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver Supersedes - © NXP B.V. 2008. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver © NXP B.V. 2008. All rights reserved ...
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... C = 1Bh) bit description . . . . . . . . . . . . . . . . . . 61 Table 49. PWR_CTRL - Power control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit allocation . . . . . . . . . . . . . . . . . . . 62 Table 50. PWR_CTRL - Power control register (address R = 3Dh to 3Fh 3Dh 3Eh, Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver continued >> © NXP B.V. 2008. All rights reserved ...
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... Table 72. Recommended bill of materials . . . . . . . . . . . .73 Table 73. SnPb eutectic process (from J-STD-020C .80 Table 74. Lead-free process (from J-STD-020C .80 Table 75. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 76. Revision history . . . . . . . . . . . . . . . . . . . . . . . .83 ISP1705_1 Product data sheet . . . . . .67 BUS Rev. 01 — 13 June 2008 ISP1705 ULPI Hi-Speed USB transceiver © NXP B.V. 2008. All rights reserved ...
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... Fig 10. Interface behavior when entering UART mode . .28 Fig 11. Interface behavior when exiting UART mode . . . .28 Fig 12. Single and back-to-back RXCMDs from the ISP1705 to the link .32 Fig 13. RXCMD A_VBUS_VLD indicator source . . . . . . .34 Fig 14. Example of register write, register read, extended register write and extended register read ...
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... HostDisconnect . . . . . . . . . . . . . . . . . . . . . . . 36 10.4 Register read and write operations . . . . . . . . 36 10.5 USB reset and high-speed detection handshake (chirp 10.6 USB packet transmit and receive . . . . . . . . . . 39 10.6.1 USB packet timing . . . . . . . . . . . . . . . . . . . . . 39 10.6.1.1 ISP1705 pipeline delays 10.6.1.2 Allowed link decision time . . . . . . . . . . . . . . . 39 10.7 Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.8 USB suspend and resume . . . . . . . . . . . . . . . 42 10.8.1 Full-speed or low-speed host-initiated suspend and resume . . . . . . . . . . . . . . . . . . . 42 10.8.2 High speed suspend and resume . . . . . . . . . 43 10 ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ISP1705 All rights reserved. Date of release: 13 June 2008 Document identifier: ISP1705_1 ...