isp1581 NXP Semiconductors, isp1581 Datasheet - Page 66

• Manufacturer Part Number: isp1581
• Description: Isp1581 Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13462
Product data
Fig 30. UDMA timing: sustained synchronous burst.
(1) DATA[15:0] and strobe signals at the receiver require some time to stabilize due to the settling time and propagation delay
DATA [ 15:0 ]
DATA [ 15:0 ]
of the cable.
IORDY
DIOR
(1)
(1)
(1)
(1)
(receiver)
(receiver)
(sender)
(sender)
14.2.4 UDMA mode
Table 79:
V
[1]
Symbol
t
t
t
t
t
t
t
su2(min)
h2(min)
su1(min)
h1(min)
w2(min)
d2(max)
d3(max)
CC
T
(= inactive) time t
be met. Since T
lengthen t
IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.
= 4.0 to 5.5 V; V
cy1
t h1
t h2
is the total cycle time, consisting of the command active time t
MDMA mode timing parameters
Parameter
data set-up time before DIOR/DIOW off
(minimum)
data hold time after DIOW off (minimum) 20
DACK set-up time before DIOR/DIOW on
(minimum)
DACK hold time after DIOR/DIOW off
(minimum)
DIOR recovery time (minimum)
DIOW recovery time (minimum)
DIOR on to DREQ off delay (maximum)
DIOW on to DREQ off delay (maximum)
DACK off to data lines three-state delay
(maximum)
w1
and/or t
Rev. 06 — 23 December 2004
cy1(min)
T cy1
w2
GND
: T
w2
cy1
is greater than the sum of t
to ensure that T
= 0 V; T
= t
t su1
w1
+ t
t su2
amb
w2
. The minimum timing requirements for T
= 40 to 85 C.
cy1
t h2
t h1
is equal to or greater than the value reported in the
[1]
[1]
…continued
w1(min)
Hi-Speed USB peripheral controller
and t
T cy1
Mode 0 Mode 1 Mode 2 Unit
100
0
20
50
215
120
40
20
w2(min)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
t su1
w1
, a host implementation must
30
15
0
5
50
50
40
40
25
and is the command recovery
t su2
cy1
, t
ISP1581
20
10
0
5
25
25
35
35
25
w1
t h1
and t
t h2
MGT507
w2
must all
ns
ns
ns
ns
ns
ns
ns
ns
ns
66 of 79