isp1581 NXP Semiconductors, isp1581 Datasheet - Page 41

• Manufacturer Part Number: isp1581
• Description: Isp1581 Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 54:
9397 750 13462
Product data
Bit
Symbol
Reset
Bus reset
Access
DMA Interrupt Enable register: bit allocation
R/W
15
-
-
9.4.8 DMA Interrupt Enable register (address: 54H)
reserved
R/W
14
Table 52:
Table 53:
[1]
This 2-byte register controls the interrupt generation of the source bits in the DMA
Interrupt Reason register (see
bit descriptions are given in
values after a (bus) reset are logic 0 (disabled).
-
-
Bit
9
8
7
6
5
4
3
2
1
0
INT_EOT
1
1
0
The short packet does not include zero-length packets.
R/W
Symbol
INTRQ_PENDING
DMA_XFER_OK
1F0_WF_E
1F0_WF_F
1F0_RF_E
READ_1F0
BSY_DONE
TF_RD_DONE
CMD_INTRQ_OK
-
13
-
-
DMA Interrupt Reason Register: bit description
Internal EOT-Functional relation with DMA_XFER_OK bit
DMA_XFER_OK Description
0
1
1
Rev. 06 — 23 December 2004
IE_ODD
_IND
R/W
12
0
0
IE_EXT_EOT
Table
Description
A logic 1 indicates that a pending interrupt was detected on
pin INTRQ.
A logic 1 indicates that the DMA transfer has been completed
(DMA Transfer Counter has become zero). This bit is only
used in GDMA (slave) mode and MDMA (master) mode.
A logic 1 indicates that the 1F0 write FIFO is empty and the
microcontroller can start writing data.
A logic 1 indicates that the 1F0 write FIFO is full and the
microcontroller must stop writing data.
A logic 1 indicates that 1F0 read FIFO is empty and the
microcontroller must stop reading data.
A logic 1 indicates that 1F0 FIFO contains unread data and
the microcontroller can start reading data.
A logic 1 indicates that the BSY status bit has become zero
and polling has been stopped.
A logic 1 indicates that the Read Task Files command has
been completed.
A logic 1 indicates that all bytes from the FIFO have been
transferred (DMA Transfer Count zero) and an interrupt on pin
INTRQ was detected.
reserved
During the DMA transfer, there is a premature termination
with short packet
DMA transfer is completed with short packet and the DMA
transfer counter has reached ‘0’.
DMA transfer is completed without any short packet and the
DMA transfer counter has reached ‘0’.
Table
R/W
11
0
0
52. A logic 1 enables interrupt generation. The
51). The bit allocation is given in
IE_INT_EOT
[1]
.
R/W
10
Hi-Speed USB peripheral controller
0
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
…continued
IE_INTRQ_
PENDING
R/W
9
0
0
ISP1581
Table
XFER_OK
IE_DMA_
R/W
54. The
8
0
0
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