isp1581 NXP Semiconductors, isp1581 Datasheet - Page 13

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isp1581

Manufacturer Part Number
isp1581
Description
Isp1581 Hi-speed Universal Serial Bus Peripheral Controller
Manufacturer
NXP Semiconductors
Datasheet

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Product data
7.4 Voltage regulators
7.5 Memory Management Unit (MMU) and integrated RAM
7.6 SoftConnect
7.7 Microcontroller/Processor Interface and
Two 5 V-to-3.3 V voltage regulators are integrated on-chip to separately supply the
analog transceiver and the internal logic. The output of these voltage regulators are
termed as V
block and the digital block, respectively. The pin V
external 1.5 k pull-up resistor on the D line.
Remark: Pins V
The MMU and the integrated RAM provide the conversion between the USB speed
(full-speed: 12 Mbit/s, high-speed: 480 Mbit/s) and the Microcontroller Handler or the
DMA Handler. The data from the USB Bus is stored in the integrated RAM, which is
cleared only when the microcontroller has read/written all data from/to the
corresponding endpoint buffer or when the DMA Handler has read/written all data
from/to the endpoint buffer. The endpoint buffer can also be cleared forcibly by setting
the CLBUF bit in the control function register. A total of 8 kbytes RAM is available for
buffering.
The connection to the USB is established by pulling the D line (for full-speed
devices) HIGH through a 1.5 k pull-up resistor. In the ISP1581 an external 1.5 k
pull-up resistor must be connected between pins RPU and V
connects the pull-up resistor to the D line, when bit SOFTCT in the Mode register is
set (see
default (SOFTCT = 0). Bit SOFTCT remains unchanged by a USB bus reset.
Microcontroller/Processor Handler
The Microcontroller Interface allows direct interfacing to most microcontrollers. The
interface is configured at power-up via inputs BUS_CONF, MODE1 and MODE0.
When BUS_CONF is set to logic 1, the Microcontroller Interface switches to the
Generic Processor mode in which AD[7:0] is the 8-bit address bus and DATA[15:0]
is the separate 16-bit data bus. If BUS_CONF is made logic 0, the interface is in the
Split Bus mode, where AD[7:0] is the local microprocessor bus (multiplexed
address/data) and DATA[15:0] is solely used as the DMA bus.
If pin MODE0 is set to logic 1, pins RD and WR are the read and write strobes (8051
style). If pin MODE0 is logic 0, pins R/W and DS pins represent the direction and data
strobe (Motorola style).
When pin MODE1 is made logic 0, ALE is used to latch the multiplexed address on
pins AD[7:0]. If pin MODE1 is set to logic 1, A0 is used to indicate address or data.
Pin MODE1 is only used in Split Bus mode: in Generic Processor mode it must be
tied to V
The Microcontroller Handler allows the external microcontroller to access the register
set in the Philips SIE as well as the DMA Handler. The initialization of the DMA
configuration is done via the Microcontroller Handler.
CC(5.0)
Table
CCA(3.3)
7). After a hardware reset the pull-up resistor is disconnected by
(logic 1).
CCA(3.3)
Rev. 06 — 23 December 2004
and V
and V
CC(3.3)
CC(3.3)
to distinguish them as being used for the analog
cannot be used to supply external devices.
Hi-Speed USB peripheral controller
CCA(3.3)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
is also used to supply an
CCA(3.3)
ISP1581
. The RPU pin
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