isp1581 NXP Semiconductors, isp1581 Datasheet - Page 20

• Manufacturer Part Number: isp1581
• Description: Isp1581 Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 9:
9397 750 13462
Product data
Bit
Symbol
Reset
Bus reset
Access
Interrupt Configuration register: bit allocation
CDBGMOD[1:0]
7
9.2.4 Interrupt Enable register (address: 14H)
R/W
03H
03H
The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow
the user to individually configure when the ISP1581 will send an interrupt to the
external microprocessor.
Bit INTPOL controls the signal polarity of the INT output (active HIGH or LOW, rising
or falling edge). For level-triggering bit INTLVL must be made logic 0. By setting
INTLVL to logic 1 an interrupt will generate a pulse of 60 ns (edge-triggering).
Table 10:
Table 11:
[1]
This register enables/disables individual interrupt sources. The interrupt for each
endpoint can be individually controlled via the associated IEPnRX or IEPnTX bits (‘n’
representing the endpoint number). All interrupts can be globally disabled via bit
GLINTENA in the Mode Register (see
An interrupt is generated when the USB SIE receives or generates an ACK or NAK
on the USB bus. The interrupt generation depends on the Debug mode settings of bit
fields CDBGMOD, DDBGMODIN and DDBGMODOUT.
Bit
7 to 6
5 to 4
3 to 2
1
0
Value
00H
01H
1XH
•
DDBGMODOUT[1:0]: interrupts for the DATA OUT endpoints 1 to 7.
6
First NAK: the first NAK on an IN or OUT token after a previous ACK response.
CDBGMOD
Interrupt on all ACK and
NAK
Interrupt on all ACK.
Interrupt on all ACK and
first NAK
Interrupt Configuration register: bit description
Debug mode settings
Symbol
CDBGMOD[1:0]
DDBGMODIN[1:0]
DDBGMODOUT[1:0]
INTLVL
INTPOL
DDBGMODIN[1:0]
5
Rev. 06 — 23 December 2004
[1]
R/W
03H
03H
Table 11
4
Description
Control 0 Debug Mode: values see
Data Debug Mode IN: values see
Data Debug Mode OUT: values see
Interrupt Level: selects the signaling mode on output
INT (0 = level, 1 = pulsed). In pulsed mode an interrupt
produces a 60 ns pulse. Bus reset value: unchanged.
Interrupt Polarity: selects signal polarity on output INT
(0 = active LOW, 1 = active HIGH). Bus reset value:
unchanged.
lists the available combinations.
DDBGMODIN
Interrupt on all ACK
and NAK
Interrupt on ACK
Interrupt on all ACK
and first NAK
DDBGMODOUT[1:0]
Table
3
7).
R/W
03H
03H
[1]
Hi-Speed USB peripheral controller
2
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
DDBGMODOUT
Interrupt on all ACK, NYET
and NAK
Interrupt on ACK and NYET
Interrupt on all ACK, NYET
and first NAK
unchanged
INTLVL
R/W
Table 11
1
0
Table 11
Table 11
ISP1581
[1]
unchanged
INTPOL
R/W
0
0
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