isp1181 NXP Semiconductors, isp1181 Datasheet - Page 63

• Manufacturer Part Number: isp1181
• Description: Isp1181 Full-speed Universal Serial Bus Interface Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 08938
Product data
20.2.1 Interrupt handling
20.2.2 Address mapping in H8S/2357
20.2.3 Using DMA
20.2 Interfacing ISP1181 with an H8S/2357 microcontroller
This section gives a summary of the ISP1181 interface with a H8S/2357 (or
compatible) microcontroller. Aspects discussed are: interrupt handling, address
mapping, DMA and I/O port usage for suspend and remote wake-up control. A typical
interface circuit is shown in
The H8S/2357 bus controller partitions its 16 Mbyte address space into eight areas
(0 to 7) of 2 Mbyte each. The bus controller will activate one of the outputs CS0 to
CS7 when external address space for the associated area is accessed.
The ISP1181 can be mapped to any address area, allowing easy interfacing when the
ISP1181 is the only device in that area. If in the example circuit for bus configuration
mode 0 (see
output CS7 of the H8S/2357 can be directly connected to input CS of the ISP1181.
The external bus specifications, bus width, number of access states and number of
program wait states can be programmed for each address area. The recommended
settings of H8S/2357 for interfacing the ISP1181 are:
The ISP1181 can be configured for several methods of DMA with the H8S/2357 and
other devices. The interface circuit in
working with the H8S/2357 in single-address DACK-only DMA mode. External
devices are not shown.
For single-address DACK-only mode, firmware must program the following settings:
•
•
•
•
•
•
ISP1181: program the Hardware Configuration register to select an active LOW
level for output INT (INTPOL = 0, see
H8S/2357: program the IRQ Sense Control Register (ISCRH and ISCRL) to
specify low-level sensing for the IRQ input.
8-bit bus in Bus Width Control Register (ABWCR)
enable wait states in Access State Control Register (ASTCR)
1 program wait state in the Wait Control Register (WCRH and WCRL).
ISP1181:
– program the DMA Counter register with the total transfer byte count
– program the Hardware Configuration Register to select active level LOW for
– select the target endpoint and transfer direction
– select DACK-only mode and enable DMA transfer.
DREQ and DACK
Figure
Rev. 04 — 30 October 2001
32) the ISP1181 is mapped to address FFFF08H (in area 7),
Figure
32.
Figure 32
Table
21)
shows an example of the ISP1181
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Full-speed USB interface
ISP1181
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