isp1181 NXP Semiconductors, isp1181 Datasheet - Page 28

• Manufacturer Part Number: isp1181
• Description: Isp1181 Full-speed Universal Serial Bus Interface Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 19:
[1]
9397 750 08938
Product data
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
Mode Register: bit allocation
DMAWD
R/W
0
7
[1]
12.1.4 Write/Read Hardware Configuration
Code (Hex): B8/B9 — write/read Mode Register
Transaction — write/read 1 byte
reserved
Table 20:
This command is used to access the Hardware Configuration Register, which
consists of 2 bytes. The first (lower) byte contains the device configuration and
control values, the second (upper) byte holds the clock control bits and the clock
division factor. The bit allocation is given in
of the programmed bit values.
The Hardware Configuration Register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA
operating mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB — write/read Hardware Configuration Register
Transaction — write/read 2 bytes
Bit
7
6
5
4
3
2
1
0
R/W
6
0
Mode Register: bit description
Symbol
DMAWD
-
GOSUSP
-
INTENA
DBGMOD
-
SOFTCT
GOSUSP
R/W
5
0
Rev. 04 — 30 October 2001
reserved
Description
A logic 1 selects 16-bit DMA bus width (bus configuration modes
0 and 2). A logic 0 selects 8-bit DMA bus width. Bus reset value:
unchanged.
reserved
Writing a logic 1 followed by a logic 0 will activate ‘suspend’
mode.
reserved
A logic 1 enables all interrupts. Bus reset value: unchanged.
A logic 1 enables debug mode. where all NAKs and errors will
generate an interrupt. A logic 0 selects normal operation, where
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints). Bus reset value:
unchanged.
reserved
A logic 1 enables SoftConnect (see
ignored if EXTPUL = 1 in the Hardware Configuration Register
(see
R/W
4
0
Table
21). Bus reset value: unchanged.
INTENA
R/W
0
3
[1]
Table
DBGMOD
21. A bus reset will not change any
R/W
0
2
[1]
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Full-speed USB interface
Section
reserved
R/W
0
1
[1]
7.4). This bit is
ISP1181
SOFTCT
R/W
0
0
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