isp1181 NXP Semiconductors, isp1181 Datasheet - Page 16

• Manufacturer Part Number: isp1181
• Description: Isp1181 Full-speed Universal Serial Bus Interface Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 08938
Product data
10.2 8237 compatible mode
Table 7:
The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware
Configuration Register (see
Table
Table 8:
The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA
controller. It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA
controller, but it is transferred between an I/O port and a memory address. A typical
example of ISP1181 in 8237 compatible DMA mode is given in
The 8237 has two control signals for each DMA channel: DRQ (DMA Request) and
DACK (DMA Acknowledge). General control signals are HRQ (Hold Request), HLDA
(Hold Acknowledge) and EOP (End-Of-Process). The bus operation is controlled via
MEMR (Memory Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).
Symbol
DREQ
DACK
EOT
RD
WR
Fig 4. ISP1181 in 8237 compatible DMA mode.
Endpoint
identifier
8.
12
13
14
Endpoint selection for DMA transfer
8237 compatible mode: pin functions
DATA1 to DATA15
Description
DMA request
DMA acknowledge
end of transfer
read strobe
write strobe
ISP1181
Rev. 04 — 30 October 2001
DREQ
DACK
EPIDX[3:0]
AD,
WR
RD
1101
1110
1111
Table
21). The pin functions for this mode are shown in
RAM
I/O
O
I
I
I
I
MEMR
MEMW
DREQ
DACK
IOR
IOW
EPDIR = 0
OUT: read
OUT: read
OUT: read
CONTROLLER
…continued
Function
ISP1181 requests a DMA transfer
DMA controller confirms the transfer
DMA controller terminates the transfer
instructs ISP1181 to put data on the bus
instructs ISP1181 to get data from the bus
DMA
8237
Transfer direction
HLDA
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
HRQ
Full-speed USB interface
Figure
HRQ
HLDA
ISP1181
EPDIR = 1
CPU
IN: write
IN: write
IN: write
MGS778
4.
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