adav400kstz-reel Analog Devices, Inc., adav400kstz-reel Datasheet - Page 30

• Manufacturer Part Number: adav400kstz-reel
• Description: Audio Codec With Embedded Sigmadsp Processor
• Manufacturer: Analog Devices, Inc.

ADAV400
Table 34. ADC Input Mux Control Register
Register Address 0x1057
Register Bits
15:4
3
2
1
0
Table 35. Power Control Register
Register Address 0x1058
Register Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
Table 36. User Control Register 2
Register Address 0x105A
Register Bits
15:8
7
6:5
4:0
0 = powered down, 1 = powered up.
Function
Reserved (set to 0)
AIN4 to ADC
AIN3 to ADC
AIN2 to ADC
AIN1 to ADC
Function
PLL
Reference buffer
ADC
VOUT4 DAC
VOUT3 DAC
VOUT2 DAC
VOUT1 DAC
AUX2 right DAC
AUX2 left DAC
AUX1/HP right DAC
AUX1/HP left DAC
Headphone amplifier right
Headphone amplifier left
SRC
Digital ADC and DAC engine
Audio processor
Function
Reserved (set to 0)
Headphone amplifier mute
Reserved (set to 0)
Headphone amplifier attenuation
0 = normal operation
1 = mute
00000 = 0 dB
00001 = −1.5 dB
00010 = −3.0 dB
….
….
11110 = −45.0 dB
11111 = −46.5 dB
1
Default = 0x0001
Default = 0x0000
Default = 0x0000
Rev. A | Page 30 of 36
Table 37. User Control Register 1
Register Address 0x1059
Register Bits
15:13
12:9
8
7
6
5:3
2:1
0
Table 38. DAC Amplifier Register
Register Address 0x110D
Register Bits
15:5
4
3:0
1
Table 39. Headphone Amplifier Register
Register Address 0x1113
Register Bits
15:1
0
1
Set this bit to 1 to obtain maximum performance from the DAC amplifier.
Set this bit to 1 to obtain maximum performance from the DAC amplifier.
Function
Reserved (set to 0)
Reserved (set to 0)
These bits read back as 0b1111
SRC mux enable
SRC lock indicator (read only)
MCLKO pin enable
MCLKO select
PLL clock select
PLL enable
Function
Reserved (set to 0)
DAC amplifier chopping
Reserved (set to 0)
Function
Reserved (set to 0)
Headphone amplifier chopping
0 = disabled
1 = enabled
0 = SRC not locked
1 = SRC locked
0 = MCLKO pin disabled
1 = MCLKO pin enabled
000 = reserved
001 = 1024 × f
010 = reserved
011 = reserved
1xx = 128 × f
00 = 64 × f
01 = 128 × f
10 = 256 × f
11 = 512 × f
0 = PLL bypassed
1 = PLL in use
0 = enabled
1 = disabled
0 = enabled
1 = disabled
Default Readback = 0x1E00
Default = 0x0000
Default = 0x0000
S
(3.072 MHz)
S
S
S
S
(6.144 MHz)
(12.288 MHz)
(24.576 MHz)
(6.144 MHz)
S
(49.152 MHz)
1
1