adav400kstz-reel Analog Devices, Inc., adav400kstz-reel Datasheet
adav400kstz-reel
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adav400kstz-reel Summary of contents
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... One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Audio Codec with ADAV400 SDO0 SDO1 SDO2 MULTICHANNEL DIGITAL OUTPUTS SDO3 LRCLK1 BCLK1 VOUT1 DAC VOUT2 VOUT3 DAC VOUT4 HPOUTL DAC HPOUTR AUXL1 AUXR1 AUXL2 DAC AUXR2 www.analog.com ©2006–2007 Analog Devices, Inc. All rights reserved. ...
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ADAV400 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Digital Timing............................................................................... 6 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 ...
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GENERAL DESCRIPTION The ADAV400 is an enhanced audio processor. Integrating high performance analog and digital I/Os with a powerful, audio- specific, programmable core enables designers to differentiate their products through audio performance. The audio processing core is based on Analog ...
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ADAV400 SPECIFICATIONS 1 AVDDn = 3.3 V, ODVDD = 3.3 V, DVDD = internal voltage regulator, temperature = 0°C to 70°C, master clock = 12.288 MHz, measurement bandwidth = kHz, ADC input signal = 1 kHz, ...
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Parameter HEADPHONE OUTPUT (SINGLE ENDED) Number of Channels Resolution Full-Scale Analog Output Dynamic Range A-Weighted Total Harmonic Distortion + Noise Gain Error Interchannel Gain Mismatch DC Offset Power Supply Rejection 3 PLL SECTION Master Clock Input (MCLKI) 3 SRC Dynamic ...
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ADAV400 DIGITAL TIMING Table 2. Parameter MASTER CLOCK AND RESET f (MCLKI Frequency) MCLKI t (MCLKI High) MCH t (MCLKI Low) MCL t (RESET Low Pulse Width) RLPW 2 I C® PORT f (SCL Clock Frequency) SCL t (SCL High) ...
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Digital Timing Diagrams t SBH BCLKx t SBL t SLH LRCLKx t SDS SDINx LEFT-JUSTIFIED MSB MODE SDOx MODE t SCH SDA SCL t MP MCLK t SDH MSB – 1 MSB t MDD t SDD Figure ...
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ADAV400 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating DVDD to DGND 2.2 V ODVDD to DGND 4.0 V AVDD to AGND 4.0 V AGND to DGND −0 +0.3 V ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS FILTA VREF AGND AVDD1 DGND DVDD AD0 SDA SCL TEST0 TEST1 DGND CONNECT Table 4. Pin Function Descriptions Pin No. Mnemonic I/O Description 1 ...
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ADAV400 Pin No. Mnemonic I/O Description 33 MCLKI I Master Clock Input. The ADAV400 uses a phase-locked loop (PLL) to generate the appropriate internal clock for the DSP core. 34 MCLKO O Audio Clock Output. The MCLKO pin can be ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0 –50 –100 –150 0 192 384 FREQUENCY (kHz) Figure 6. DAC Composite Filter Response (48 kHz) 0 –50 –100 –150 FREQUENCY (kHz) Figure 7. DAC Pass-Band Filter Response (48 kHz) 0.06 0.04 0.02 ...
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ADAV400 0 –20 –40 –60 –80 –100 –120 –140 –160 0 4000 8000 12000 FREQUENCY (Hz) Figure 12. DAC Dynamic Range 0 –20 –40 –60 –80 –100 –120 –140 –160 0 4000 8000 12000 FREQUENCY (Hz) Figure 13. DAC Total ...
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THEORY OF OPERATION The ADAV400 is an enhanced audio processor containing an Analog Devices SigmaDSP digital processing core. The core can accept up to four digital stereo channels, typically at 48 kHz, or three channels, typically at 48 kHz, and ...
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ADAV400 HEADPHONE AMPLIFIER The ADAV400 has an integrated stereo headphone amplifier capable of driving 32 mW into a 32 Ω load. VOLTAGE REGULATOR The ADAV400 includes an on-chip voltage regulator that enables the chip to be used in systems where ...
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CONTROL PORT The ADAV400 control port has full read and write capability to all registers and RAMs with the exception of the data RAM, which is only accessible by the DSP core. Single or burst mode reads and writes are ...
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ADAV400 Read and Write Operations Table 6 shows the timing of a single word write operation. Every ninth clock, the ADAV400 issues an acknowledge by pulling SDA low. Table 7 shows the timing of a burst mode ...
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SCL SDA START BY MASTER FRAME 1 CHIP ADDRESS BYTE SCL (CONTINUED) SDA (CONTINUED) FRAME 2 SUBADDRESS BYTE 2 SCL 1 1 SDA START BY MASTER FRAME 1 CHIP ADDRESS BYTE SCL (CONTINUED) ...
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ADAV400 SIGNAL PROCESSING The ADAV400 is designed to provide all the signal processing functions commonly used in stereo or multichannel playback systems. The signal processing flow is created using a graphical development tool supplied by Analog Devices, which allows fast ...
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RAMS AND REGISTERS Table 10. Control Port Addresses Subaddress Register Name 0 to 1023 (0x0000 to 0x03FF) Parameter RAM 1024 to 3584 (0x0400 to 0x0E00) Program RAM 4096 to 4159 (0x1000 to 0x103F) Target/slew RAM 4160 to ...
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ADAV400 RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURES When writing large amounts of data to the program or parameter RAM in direct write mode, disable the processor core to prevent pops or clicks in the audio output. The ADAV400 contains several mechanisms for ...
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Table 14. Target/Slew RAM Ramp Type Settings Settings Ramp Type 00 Linear 01 Constant Constant time The following sections detail how the control port writes to the target/slew RAM to control the time constant and ramp ...
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ADAV400 Constant dB and RC Updates (Exponential) An exponential update is accomplished by shifts and additions with a range from 6 1.27 sec (−60 dB relative full scale). When the ramp type is set to ...
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TIME (ms) Figure 30. Slew RAM—Constant Time Update Decreasing Ramp, Full Scale SAFE LOAD REGISTERS Many applications require real-time control of signal processing parameters, ...
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ADAV400 CONTROL PORT READ/WRITE DATA FORMATS The read/write formats of the control port are designed to be byte oriented. To conform to this byte-oriented format, 0s are appended to the data fields before the MSB to extend the data- word ...
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Table 23. Data Capture (Control Port Readback) Register Read Format Byte 0 Byte 1 chip_adr [6:0], R/W 000, data_capture_adr [12:8] Table 24. Safe Load Register Data Write Format Byte 0 Byte 1 chip_adr [6:0], R/W 000, safeload_adr [12:8] Table 25. ...
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ADAV400 SERIAL DATA INPUT/OUTPUT PORTS The flexible serial data input/output ports of the ADAV400 can be set to accept or transmit data in 2-channel format 16-channel TDM stream. Data is processed in twos complement, MSB-first ...
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LEFT CHANNEL LRCLK BCLK MSB SDATA LEFT CHANNEL LRCLK BCLK MSB SDATA Figure 32. Left-Justified Mode— Bits per Channel LEFT CHANNEL LRCLK BCLK SDATA MSB Figure 33. Right-Justified Mode— Bits per Channel LRCLK BCLK 32 BCLKs ...
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ADAV400 CONTROL REGISTERS Table 28. Audio Register Map Register Address (Hex) 0x1052 0x1053 0x1054 0x1055 0x1056 0x1057 0x1058 0x1059 0x105A 0x110D 0x1113 Table 29. Audio Core Control Register Register Address 0x1052 Default Readback = 0x4000 Register Bits Function 15 Reserved ...
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Table 30. RAM Modulo Control Register (Eight Bits) Register Address 0x1053 Default = 0x28 Register Bits Function 7:6 Reserved (set to 0) 5:0 RAM modulo size (1 LSB = 512 locations) Table 31. Serial Output Control Register Register Address 0x1054 ...
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ADAV400 Table 34. ADC Input Mux Control Register Register Address 0x1057 Default = 0x0001 Register Bits Function 15:4 Reserved (set AIN4 to ADC 2 AIN3 to ADC 1 AIN2 to ADC 0 AIN1 to ADC Table 35. ...
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AUDIO CORE CONTROL REGISTER The bits in this register control the operation of the DSP core of the ADAV400 (see Table 29). Enable SDO2 and SDO3 (Bit 14) This bit is set default and can be used ...
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ADAV400 RAM MODULO CONTROL REGISTER The ADAV400 uses a modulo RAM addressing scheme that allows very efficient coding of filters and other blocks by automatically incrementing the data RAM pointer at the end of each sample period. This works well ...
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Table 27 can also be used to verify register settings for each serial data format. SRC SERIAL PORT CONTROL REGISTER SRC Serial Input Port Select (Bits [6:5]) These bits select which of the four serial data inputs are directed to ...
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ADAV400 TYPICAL APPLICATION DIAGRAM 600Z + + 47µF 600Z 20kΩ + VIN1L AINL1 100nF 47µF 600Z 20kΩ + VIN4R AINR4 100nF BCLK0 LRCLK0 BCLK1 LRCLK1 SDIN0 TO AUDIO SDIN1 CONTROLLER SDIN2 SDIN3 SDO0 SDO1 SDO2 SDO3 RESET RESET CIRCUITRY CLOCK ...
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... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 ADAV400KSTZ 0°C to 70°C 1 ADAV400KSTZ-REEL 0°C to 70°C 1 EVAL-ADAV400EBZ RoHS Compliant Part. 16.20 16.00 SQ 0.75 1.60 15.80 0.60 MAX 0. PIN 1 TOP VIEW (PINS DOWN) 0.20 0.09 7° 3.5° 20 0° 21 0.10 COPLANARITY VIEW A 0.65 BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BEC Figure 38 ...
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... ADAV400 NOTES ©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05811-0-7/07(A) Rev Page ...