ADAV400 Analog Devices, ADAV400 Datasheet
ADAV400
Related parts for ADAV400
ADAV400 Summary of contents
Page 1
... V (digital interface) TV audio processing Set top box (STB) HTiB SDO0 SDO1 SDO2 MULTICHANNEL DIGITAL OUTPUTS SDO3 LRCLK1 BCLK1 VOUT1 DAC VOUT2 VOUT3 DAC VOUT4 HPOUTL DAC HPOUTR AUXL1 AUXR1 AUXL2 DAC AUXR2 ©2006 Analog Devices, Inc. All rights reserved. ADAV400 www.analog.com ...
Page 2
... ADAV400 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Digital Timing............................................................................... 6 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 13 Analog Inputs.............................................................................. 13 Sample Rate Converter Block ................................................... 13 PLL Block..................................................................................... 13 Analog Outputs........................................................................... 13 Headphone Amplifier ................................................................ 14 Voltage Regulator ...
Page 3
... GENERAL DESCRIPTION The ADAV400 is an enhanced audio processor. Integrating high performance analog and digital I/Os with a powerful, audio- specific, programmable core enables designers to differentiate their products through audio performance. The audio processing core is based on Analog Devices SigmaDSP technology featuring full 28-bit processing (56-bit in double precision mode), a sophisticated, fully programmable dynamics processor, and delay memory ...
Page 4
... ADAV400 SPECIFICATIONS 1 AVDDn = 3.3 V, ODVDD = 3.3 V, DVDD = internal voltage regulator, temperature = 0°C to 70°C, master clock = 12.288 MHz, measurement bandwidth = kHz, ADC input signal = 1 kHz, DAC output signal = 1 kHz, unless otherwise noted. Table 1. Parameter REFERENCE SECTION Absolute Voltage V REF V Temperature Coefficient ...
Page 5
... Rev Page ADAV400 Test Conditions/Comments Measured at headphone output with 32 Ω load, headphone amplifier register contents = 0x0001 One stereo channel −60 dBFS with respect to full-scale code input −3 dBFS with respect to full-scale code input Relative to V REF 1 1 kHz, 300 mV p-p signal at AVDDn − ...
Page 6
... ADAV400 DIGITAL TIMING Table 2. Parameter MASTER CLOCK AND RESET f (MCLKI Frequency) MCLKI t (MCLKI High) MCH t (MCLKI Low) MCL ( RESET Low Pulse Width) t RLPW PORT f (SCL Clock Frequency) SCL t (SCL High) SCLH t (SCL Low) SCLL Start Condition t (Setup Time) SCS t (Hold Time) ...
Page 7
... SCL t MP MCLK t SDH MSB – 1 MSB t MDD t SDD Figure 2. Serial Port Timing t t SDR SCR SCLH t t SCLL SCF 2 Figure Port Timing Figure 4. Master Clock Timing Rev Page SLH t t SCH SDF t t SCS SCSH ADAV400 ...
Page 8
... ADAV400 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating DVDD to DGND 2.2 V ODVDD to DGND 4.0 V AVDD to AGND 4.0 V AGND to DGND −0 +0.3 V Digital Inputs DGND − 0 ODVDD + 0.3 V Analog Inputs AGND − 0 ADVDD + 0.3 V Reference Voltage Indefinite short-circuit to ground Soldering (10 sec) 300° ...
Page 9
... Scale Figure 5. Pin Configuration 2 C Control Port Control Port. Rev Page ADAV400 VOUT3 60 VOUT2 59 VOUT1 58 AUXR1 57 AUXL1 56 AVDD3 55 54 HPOUTR HPOUTL 53 AGND 52 AGND ...
Page 10
... Bit Clock for Serial Data Input/Output. This clock and the LRCLK1 are used as clock and frame sync signals for the SDINx and SDOx pins. These clocks are inputs to the ADAV400 when the port is configured as a slave, and outputs when the port is configured as a master. On power up, these pins are set to slave mode to avoid conflicts with external master mode devices ...
Page 11
... Rev Page –50 0 128 256 FREQUENCY (kHz) Figure 9. ADC Composite Filter Response (48 kHz) 0 – FREQUENCY (kHz) Figure 10. ADC Pass-Band Filter Response (48 kHz FREQUENCY (kHz) Figure 11. ADC Pass-Band Ripple (48 kHz) ADAV400 384 96 24 ...
Page 12
... ADAV400 0 –20 –40 –60 –80 –100 –120 –140 –160 0 4000 8000 12000 FREQUENCY (Hz) Figure 12. DAC Dynamic Range 0 –20 –40 –60 –80 –100 –120 –140 –160 0 4000 8000 12000 FREQUENCY (Hz) Figure 13. DAC Total Harmonic Distortion + Noise 0 –20 –40 –60 –80 –100 –120 – ...
Page 13
... ADAV400 can be configured left-justified, right-justified, or TDM serial port-compatible mode. They can support 16, 20 bits in all modes. The ADAV400 accepts serial audio data in MSB-first and twos complement formats. The digital core of the ADAV400 operates at 1.8 V, and the other circuit blocks operate from a 3.3 V power supply. An on- board regulator allows a single 3 ...
Page 14
... Figure 19. Here, VDD is the main system voltage (3.3 V). A voltage of 1 generated at the transistor’s collector and is connected to the DVDD pins. VDRIVE is an output from the internal regulator circuit on the ADAV400 and is connected to the base of the PNP transistor VDD + Figure 19. Voltage Regulator Design There are two specifications to take into consideration when choosing the regulator’ ...
Page 15
... Logic Level 1 corresponds to a read operation, and Logic Level 0 corresponds to a write operation. The seventh bit of the address is set by tying the AD0 pin of the ADAV400 to Logic Level 0 or Logic Level 1. Table 5. I AD0 ...
Page 16
... Other address ranges may have a variety of word lengths ranging from one to six bytes; the ADAV400 always decodes the subaddress and sets the auto-increment circuit so that the address increments after the appropriate number of bytes. ...
Page 17
... ACK. BY REPEATED ADAV400 START BY MASTER ACK. BY MASTER READ DATA BYTE 1 2 Figure 21 Read Format Rev Page ADAV400 ACK. BY ADAV400 FRAME 2 ACK. BY STOP BY ADAV400 MASTER FRAME 3 DATA BYTE 1 ACK. BY ADAV400 FRAME 2 ADR R/W SEL ACK. BY ADAV400 FRAME 4 CHIP ADDRESS BYTE ACK ...
Page 18
... The signal processing blocks can be arranged in a custom program that is loaded to the RAM of the ADAV400. The available signal processing blocks are outlined in the Numeric Formats and Programming sections. ...
Page 19
... To avoid clicks or pops, mute the DSP core first. CONTROL PORT ADDRESSING Table 10 shows the addressing of the RAM and register spaces on the ADAV400. The address space encompasses a set of registers and three RAMs: parameter, program, and target\slew. Table 11 lists the sizes and available writing modes of the parameter, program, and target/slew RAMs ...
Page 20
... When writing large amounts of data to the program or parameter RAM in direct write mode, disable the processor core to prevent pops or clicks at the audio output. The ADAV400 contains several mechanisms for disabling the core. If the loaded program does not use the target/slew RAM as the ...
Page 21
... CONST 10 20 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 TIME (ms) Figure 23. Slew RAM—Linear Update Increasing Ramp 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 TIME (ms) Figure 24. Slew RAM—Linear Update Decreasing Ramp ADAV400 ...
Page 22
... ADAV400 Constant dB and RC Updates (Exponential) An exponential update is accomplished by shifts and additions with a range from 6 1.27 sec (−60 dB relative full scale). When the ramp type is set to 01 (constant dB), each step size is set to the current value in the slew data. When the ramp ...
Page 23
... Data capture registers are used for debugging user-programmed blocks and are not required when using pre-existing library blocks. The ADAV400 data capture feature allows the data at any node in the signal processing flow to be sent to one of six control- port-readable registers serial output pin. Use this feature to monitor and display information about internal signal levels or compressor/limiter activity ...
Page 24
... A burst mode write is done by writing the address and data of the first RAM/register location to be written followed by the next data-word, and so on. The ADAV400 control port auto- increments the internal address counter depending on the location being written to or read from, even across the boundaries of the different RAMs and registers locations ...
Page 25
... Table 24. Safeload Register Data Write Format Byte 0 Byte 1 chip_adr [6:0], R/W 000, safeload_adr [12:8] Table 25. Safeload Register Address Write Format Byte 0 Byte 1 chip_adr [6:0], R/W 000, safeload_adr [12:8] Byte 2 Byte 3 safeload_adr [7:0] 000000, data [33:32] Byte 2 Byte 3 safeload_adr [7:0] 0000, param_adr [11:8] Rev Page ADAV400 Bytes data [31:0] Byte 4 param_adr [7:0] ...
Page 26
... Table 26. There are two modes of operation. In both 8-channel and 16-channel TDM modes, SDIN0 is the input for the TDM stream and SDO0 is the output. Figure 34 shows the ADAV400 operating in TDM mode. Refer to the Serial Data Input/Output Ports section for a more complete description of the modes of operation. ...
Page 27
... MSB–2 DATA Figure 34. 8-Channel TDM Mode with Clock SLOT 2 SLOT 3 SLOT 4 SLOT 5 SDIN1L SDIN1R SDIN2L SDIN2R Figure 35. TDM Mode with Pulse Word Clock Rev Page ADAV400 LSB RIGHT CHANNEL LSB RIGHT CHANNEL LSB SLOT 7 MSB TDM 8TH CH SLOT 6 SLOT 7 SDIN3L ...
Page 28
... ADAV400 CONTROL REGISTERS Table 28. Audio Register Map Register Address (Hex) 0x1052 0x1053 0x1054 0x1055 0x1056 0x1057 0x1058 0x1059 0x105A 0x110D 0x1113 Table 29. Audio Core Control Register Register Address 0x1052 Default Readback = 0x4000 Register Bits Function 15 Reserved (set Enable SDO2 and SDO3 ...
Page 29
... Serial input mode 000 = I 001 = left-justified 010 = reserved 011 = right-justified, 24 bits 100 = right-justified, 20 bits 101 = right-justified, 18 bits 110 = right-justified, 16 bits All others are reserved Rev Page ADAV400 Default = 0x00 2 S Default = 0x00 2 S ...
Page 30
... ADAV400 Table 34. ADC Input Mux Control Register Register Address 0x1057 Default = 0x0001 Register Bits Function 15:4 Reserved (set AIN4 to ADC 2 AIN3 to ADC 1 AIN2 to ADC 0 AIN1 to ADC Table 35. Power Control Register Register Address 0x1058 Default = 0x0000 1 Register Bits Function 15 PLL 14 Reference buffer ...
Page 31
... Setting this bit to 0 sets the contents of the accumulators and serial output registers to 0. This bit defaults to 0; therefore, the ADAV400 powers up in clear mode and does not pass signals until written to this bit. This is intended to prevent noises from inadvertently occurring during the power-up sequence. ...
Page 32
... The serial input port can also operate with LRCLK1 as a pulse, rather than a clock. In this case, the first edge of the pulse is used by the ADAV400 to start the data frame. When the polarity bit is set to 0, data is clocked in on the falling edge of LRCLK1; when this bit is set to 1, data is clocked in on the rising edge ...
Page 33
... POWER CONTROL REGISTER Power Control (Bits [15:0]) These bits can individually power up or power down the different blocks of the ADAV400. USER CONTROL REGISTER 2 Headphone Amplifier Mute (Bit 7) When set, this bit mutes the analog headphone amplifier. Headphone Amplifier Attenuation (Bits [4:0]) These bits set the analog gain of the headphone amplifier. It can be set in steps of − ...
Page 34
... SDO2 SDO3 RESET RESET CIRCUITRY CLOCK MCLKI SDA SCL CONTROLLER AD0 3.3V 3.3V 10µF FZT953 + 100nF + + + ADAV400 Figure 37. Typical Application Circuit Rev Page 47µF 560Ω + VOUT1 VOUT1 5.6nF 47µF 560Ω + VOUT4 VOUT4 5.6nF 47µF 560Ω + AUXL1 AUXL1 5.6nF 47µ ...
Page 35
... The ADAV400 is a Pb-free, environmentally friendly product manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and can withstand surface-mount soldering 255°C (±5°C). In addition backward-compatible with conventional Sn/Pb soldering processes. This means the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220° ...
Page 36
... ADAV400 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05811–0–1/06(0) Rev Page ...