adav801 Analog Devices, Inc., adav801 Datasheet - Page 55

• Manufacturer Part Number: adav801
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

PLL Clock Source Register—Address 1111000 (0x78)
Table 136. PLL Clock Source Register Bit Map
7
PLL2_Source
Table 137. PLL Clock Source Register Bit Descriptions
Bit Name
PLL2_Source
PLL1_Source
PLL Output Enable—Address 1111010 (0x7A)
Table 138. PLL Output Enable Register Bit Map
7
Reserved
Table 139. PLL Output Enable Register Bit Descriptions
Bit Name
DIRINPD
DIRIN_PIN
SYSCLK1
SYSCLK2
SYSCLK3
6
PLL1_Source
6
Reserved
Description
Selects the clock source for PLL2.
Selects the clock source for PLL1.
Description
This bit powers down the S/PDIF receiver.
This bit determines the input levels of the DIRIN pin.
Enables the SYSCLK1 output.
Enables the SYSCLK2 output.
Enables the SYSCLK3 output.
0 = XIN.
1 = MCLKI.
0 = XIN.
1 = MCLKI
0 = Normal.
1 = Power-down.
0 = DIRIN accepts input signals down to 200 mV according to AES3 requirements.
1 = DIRIN accepts input signals as defined in the Specifications section.
0 = Enabled.
1 = Disabled.
0 = Enabled.
1 = Disabled.
0 = Enabled.
1 = Disabled.
5
Reserved
5
DIRINPD
4
Reserved
4
DIRIN_PIN
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3
Reserved
3
Reserved
2
Reserved
2
SYSCLK1
1
Reserved
1
SYSCLK2
0
Reserved
0
SYSCLK3
ADAV801