adav801 Analog Devices, Inc., adav801 Datasheet - Page 44

• Manufacturer Part Number: adav801
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

ADAV801
Receiver User Bit Buffer Indirect Address— Address 1010000 (0x50)
Table 81. Receiver User Bit Buffer Indirect Address Register Bit Map
7
RxUBADDR7
Table 82. Receiver User Bit Buffer Indirect Address Register Bit Descriptions
Bit Name
RxUBADDR[7:0]
Receiver User Bit Buffer Data—Address 1010001 (0x51)
Table 83. Receiver User Bit Buffer Data Register Bit Map
7
RxUBDATA7
Table 84. Receiver User Bit Buffer Data Register Bit Descriptions
Bit Name
RxUBDATA[7:0]
Transmitter User Bit Buffer Indirect Address—Address 1010010 (0x52)
Table 85. Transmitter User Bit Buffer Indirect Address Register Bit Map
7
TxUBADDR7
Table 86. Transmitter User Bit Buffer Indirect Address Register Bit Descriptions
Bit Name
TxUBADDR[7:0]
Transmitter User Bit Buffer Data—Address 1010011 (0x53)
Table 87. Transmitter User Bit Buffer Data Register Bit Map
7
TxUBDATA7
Table 88. Transmitter User Bit Buffer Data Register Bit Descriptions
Bit Name
TxUBDATA[7:0]
Q Subcode CRCError Status—Address 1010100 (0x54)
Table 89. Q Subcode CRCError Status Register (Read-Only) Bit Map
7
Reserved
Table 90. Q Subcode CRCError Status Register (Read-Only) Bit Descriptions
Bit Name
QCRCERROR
QSUB
6
RxUBADDR6
6
RxUBDATA6
6
TxUBADDR6
6
TxUBDATA6
6
Reserved
Description
Indirect address pointing to the address location in the receiver user bit buffer.
Description
A read from this register reads eight bits of user data from the receiver user bit buffer pointed to by RxUBADDR0[7:0].
This buffer can be written to when autobuffering of the user bits is enabled; otherwise, it is a read-only buffer.
Description
Indirect address pointing to the address location in the transmitter user bit buffer.
Description
A write to this register writes eight bits of user data to the transmit user bit buffer pointed to by TxUBADDR0[7:0].
When user bit autobuffering is enabled, this buffer is disabled.
Description
This bit is set if the CRC check of the Q subcode fails. This bit remains high, but does not generate an interrupt. This
bit is cleared once the register is read.
This bit is set if a Q subcode has been read into the Q subcode buffer (see Table 91).
5
RxUBADDR5
5
RxUBDATA5
5
TxUBADDR5
5
TxUBDATA5
5
Reserved
4
RxUBADDR4
4
RxUBDATA4
4
TxUBADDR4
4
TxUBDATA4
4
Reserved
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3
RxUBADDR3
3
RxUBDATA3
3
TxUBADDR3
3
TxUBDATA3
3
Reserved
2
RxUBADDR2
2
RxUBDATA2
2
TxUBADDR2
2
TxUBDATA2
2
Reserved
1
RxUBADDR1
1
RxUBDATA1
1
TxUBADDR1
1
TxUBDATA1
1
QCRCERROR
0
RxUBADDR0
0
RxUBDATA0
0
TxUBADDR0
0
TxUBDATA0
0
QSUB