adav801 Analog Devices, Inc., adav801 Datasheet
adav801
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adav801 Summary of contents
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... Device control via SPI-compatible serial port 64-lead LQFP package GENERAL DESCRIPTION The ADAV801 is a stereo audio codec intended for applications such as DVD or CD recorders that require high performance and flexible, cost-effective playback and record functionality. The ADAV801 features Analog Devices, Inc. proprietary, high performance converter cores to provide record (ADC), playback (DAC), and format conversion (SRC single chip ...
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... ADAV801 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Test Conditions............................................................................. 3 ADAV801 Specifications ............................................................. 3 Timing Specifications .................................................................. 7 Temperature Range ...................................................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Functional Description .................................................................. 15 ADC Section ............................................................................... 15 REVISION HISTORY 7/07—Rev Rev. A Changes to Table 1 ...
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... Ambient Temperature Master Clock (MCLKI) Measurement Bandwidth Word Width (All Converters) Load Capacitance on Digital Outputs ADC Input Frequency DAC Output Frequency Digital Input Digital Output ADAV801 SPECIFICATIONS Table 2. Parameter PGA SECTION Input Impedance Minimum Gain Maximum Gain Gain Step REFERENCE SECTION ...
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... ADAV801 Parameter Crosstalk (EIAJ Method) Volume Control Step Size (256 Steps) Maximum Volume Attenuation Mute Attenuation Group Delay kHz kHz S ADC LOW-PASS DIGITAL DECIMATION FILTER 1 CHARACTERISTICS Pass-Band Frequency Stop-Band Frequency Stop-Band Attenuation Pass-Band Ripple ADC HIGH-PASS DIGITAL FILTER CHARACTERISTICS ...
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... DVDD V 0 μA 10 μA 2 Rev Page ADAV801 Comments f = 44.1 kHz kHz kHz 44.1 kHz kHz kHz 44.1 kHz kHz kHz 44.1 kHz ...
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... ADAV801 Parameter POWER Supplies Voltage, AVDD Voltage, DVDD Voltage, ODVDD Operating Current Analog Current Digital Current Digital Interface Current DIRIN/DIROUT Current PLL Current Power-Down Current Analog Current Digital Current Digital Interface Current DIRIN/DIROUT Current PLL Current Power Supply Rejection Signal at Analog Supply Pins 1 Guaranteed by design ...
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... From xBCLK rising edge ns To xBCLK rising edge ns From xBCLK rising edge ns From xBCLK falling edge 5 ns From xBCLK falling edge 10 ns From xBCLK falling edge ns From xBCLK rising edge ns From xBCLK rising edge Max Unit °C +85 °C +150 °C ADAV801 ...
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... ADAV801 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating DVDD to DGND and ODVDD 4.6 V DGND AVDD to AGND 4.6 V Digital Inputs DGND − 0 DVDD + 0.3 V Analog Inputs AGND − 0 AVDD + 0.3 V AGND to DGND −0 +0.3 V Reference Voltage Indefinite short circuit to ground Soldering (10 sec) 300° ...
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... DGND Figure 2. ADAV801 Pin Configuration Description Analog Audio Input, Right Channel. Analog Audio Input, Left Channel. Analog Ground. Analog Voltage Supply. DIR Phase-Locked Loop (PLL) Filter Pin. Supply Ground for DIR Analog Section. This pin should be connected to AGND. ...
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... ADAV801 Pin No. Mnemonic I/O 27 OAUXLRCLK I/O 28 OAUXBCLK I/O 29 OAUXSDATA O 30 IAUXLRCLK I/O 31 IAUXBCLK I/O 32 IAUXSDATA I 33 DGND 34 DVDD 35 MCLKI I 36 MCLKO O 37 XOUT I 38 XIN I 39 SYSCLK3 O 40 SYSCLK2 O 41 SYSCLK1 O 42 DGND 43 PLL_VDD 44 PLL_GND 45 PLL_LF1 46 PLL_LF2 47 ADGND 48 ADVDD 49 VOUTR VOUTL AVDD ...
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... S 0.06 0.04 0.02 0 –0.02 –0.04 –0. kHz S Rev Page 192 288 FREQUENCY (kHz) Figure 6. DAC Composite Filter Response, 48 kHz FREQUENCY (kHz) Figure 7. DAC Pass-Band Filter Response, 48 kHz FREQUENCY (kHz) Figure 8. DAC Filter Ripple, 48 kHz ADAV801 384 48 24 ...
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... ADAV801 0 –50 –100 –150 0 192 384 FREQUENCY (kHz) Figure 9. DAC Composite Filter Response, 96 kHz 0 –50 –100 –150 FREQUENCY (kHz) Figure 10. DAC Pass-Band Filter Response, 96 kHz 0.10 0.05 0 –0.05 –0. FREQUENCY (kHz) Figure 11. DAC Filter Ripple, 96 kHz 0 –50 –100 –150 –200 0 576 ...
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... DNR = 102dB (A-WEIGHTED) –20 –40 –60 –80 –100 –120 –140 –160 Rev Page ADAV801 THD+N = 95dB FREQUENCY (kHz) Figure 18. DAC THD + kHz S DNR = 102dB (A-Weighted FREQUENCY (kHz) Figure 19. ADC Dynamic Range, f ...
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... ADAV801 0 –20 –40 –60 –80 –100 –120 –140 –160 FREQUENCY (kHz) Figure 21. ADC Dynamic Range, f DNR = 102dB (A-WEIGHTED) –100 –120 –140 –160 kHz S Rev Page –20 –40 –60 – FREQUENCY (kHz) Figure 22. ADC THD + N, f ...
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... FUNCTIONAL DESCRIPTION ADC SECTION The ADAV801’s ADC section is implemented using a second- order multibit (5 bits) Σ-Δ modulator. The modulator is sampled at either half of the ADC MCLK rate (modulator clock = 128 × one-quarter of the ADC MCLK rate (modulator S clock = 64 × The digital decimator consists of a Sinc^5 filter S followed by a cascade of three half-band FIR filters ...
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... ADAV801 Automatic Level Control (ALC) The ADC record channel features a programmable automatic level control block. This block monitors the level of the ADC output signal and automatically reduces the gain, if the signal at the input pins causes the ADC output to exceed a preset limit. ...
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... For best performance of the ADC, avoid using similar frequency clocks from separate sources in the ADAV801. For example, running the ADC from a 12.288 MHz clock connected to MCLKI and using the PLL to generate a separate 12.288 MHz clock for the DAC can reduce the performance of the ADC ...
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... ADAV801 DAC SECTION The ADAV801 has two DAC channels arranged as a stereo pair with single-ended analog outputs. Each channel has its own independently programmable attenuator, adjustable in 128 steps of 0.375 dB per step. The DAC can receive data from the playback or auxiliary input ports, the SRC, the ADC, or the DIR ...
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... Because the ratio irrational number, the error resulting from the resampling at f can never be eliminated. The error can be significantly S_OUT reduced, however, through interpolation of the input data Therefore, the sample rate converter in the ADAV801 is S_IN conceptually interpolated by a factor of 2 ZERO-ORDER IN HOLD f ...
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... ADAV801 The worst-case images can be computed from the zero-order hold frequency response: Maximum Image = sin(π × F/f S_INTERP where the frequency of the worst-case image that would × f ± f /2. S_IN S_IN × S_INTERP S_IN The following worst-case images would appear for f ...
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... The ratio is S_IN S_OUT S_OUT counter > the ratio is held at one. S_IN S_OUT S_IN , the sample rate ratio is updated different S_OUT periods from the previous f S_OUT ADAV801 > S_IN 20 ) × 2 ratio for 10k 100k /f S_IN S_OUT counter to the to f S_OUT ...
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... PLL clock values, PLL1 and PLL2, are selected. The clock nodes, PLL1 and PLL2, can be used as master clocks for the other blocks in the ADAV801, such as the DAC or ADC. The PLL has separate supply and ground pins, which should be as clean as possible to prevent electrical noise from being converted into clock jitter by coupling onto the loop filter pins ...
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... VCO of the clock recovery PLL. The recovered audio data and audio clock can be routed to the different blocks of the ADAV801, as required. Figure 39 shows a conceptual diagram of the DIRIN block. REG 0x7A ...
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... CP-2401). The organization of the channel status block, frames, and subframes is shown in Table 9 and Table 10. Note that the ADAV801 supports the professional audio standard from a software point of view only. The digital interface supports only consumer mode ...
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... Receiver Section The ADAV801 uses a double-buffering scheme to handle read- ing channel status and user bit information. The channel status bits are available as a memory buffer, taking up 24 consecutive register locations. The user bits are read using an indirect ...
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... ADAV801 The size of the user bit buffer can be set by programming the RxBCONF0 bit in the receiver buffer configuration register, as shown in Table 11. Table 11. RxBCONF3 Functionality RxBCONF0 Receiver User Bit Buffer Size 0 384 bits with Preamble Z as the start of the block. 1 768 bits with Preamble Z as the start of the block. ...
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... Pin functions as an interrupt pin. SERIAL DATA PORTS The ADAV801 contains four flexible serial ports (SPORTs) to allow data transfer to and from the codec. All four SPORTs are independent and can be configured as master or slave ports. In slave mode, the xLRCLK and xBCLK signals are inputs to the serial ports ...
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... Figure timing diagram of REG 0x04 the serial data port formats. BITS[4:3] Clocking Scheme The ADAV801 provides a flexible choice of on-chip and off- SRC chip clocking sources. The on-chip oscillator with dual PLLs is MCLK intended to offer complete system clocking requirements for ...
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... Datapath The ADAV801 features a digital input/output switching/ multiplexing matrix that gives flexibility to the range of possible input and output connections. Digital input ports include playback and auxiliary input (both 3-wire digital), and S/PDIF (single-wire to the on-chip receiver). Output ports include the record and auxiliary output ports (both 3-wire digital) and the S/PDIF port (single-wire from the on-chip transmitter) ...
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... COUT 8 BITS BLOCK READS AND WRITES The ADAV801 provides the user with the ability to write to or read from a block of registers in one continuous operation. In SPI mode, the CLATCH line should be held low for longer than the 16 CCLK periods to use the block read/write mode. For a ...
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... Table 20. S/PDIF Loopback Control Register Bit Descriptions Bit Name Description TxMUX Selects the source for S/PDIF output (DITOUT S/PDIF transmitter, normal mode DIRIN, loopback mode CLK2DIV0 CLK1DIV1 CLK1DIV0 ). Reserved Reserved Reserved Rev Page ADAV801 1 0 MCLKSEL1 MCLKSEL0 1 0 Reserved TxMUX ...
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... ADAV801 Playback Port Control—Address 0000100 (0x04) Table 21. Playback Port Control Register Bit Map Reserved Reserved Reserved Table 22. Playback Port Control Register Bit Descriptions Bit Name Description CLKSRC[1:0] Selects the clock source for generating the ILRCLK and IBCLK Input port is a slave. ...
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... Selects the serial output word length bits bits bits bits. SPMODE[1:0] Selects the serial format of the auxiliary record port Left-justified Reserved Right-justified CLKSRC0 WLEN1 WLEN0 CLKSRC0 WLEN1 WLEN0 Rev Page ADAV801 1 0 SPMODE1 SPMODE0 1 0 SPMODE1 SPMODE0 ...
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... ADAV801 Group Delay and Mute—Address 0001000 (0x08) Table 29. Group Delay and Mute Register Bit Map MUTE_SRC GRPDLY6 GRPDLY5 Table 30. Group Delay and Mute Register Bit Descriptions Bit Name Description MUTE_SRC Soft-mutes the output of the sample rate converter mute. ...
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... When the NO_VALIDITY bit is set, data from the AES3/S/PDIF receiver is not allowed into the SRC AES3/S/PDIF receiver data is sent to the SRC Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO_VALIDITY bit is set SP_PLL_ SEL0 Reserved Reserved Rev Page ADAV801 NONAUDIO NO_VALIDITY ...
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... ADAV801 Receiver Buffer Configuration—Address 0001011 (0x0B) Table 35. Receiver Buffer Configuration Register Bit Map Reserved Reserved RxBCONF5 Table 36. Receiver Buffer Configuration Register Bit Descriptions Bit Name Description RxBCONF5 If the user bits are formatted according to the IEC60958-3 standard and the DAT category is detected, the user bit interrupt is enabled only when there is a change in the start (ID) bit ...
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... Receiver Channel Status A buffer can be accessed at address locations 0x20 through 0x37 24-byte Receiver Channel Status B buffer can be accessed at address locations 0x20 through 0x37 IU_Zeros0 TxBCONF3 TxBCONF2 Disable_Tx_Copy Reserved Reserved Rev Page ADAV801 1 0 TxBCONF1 TxBCONF0 1 0 TxCSSWITCH RxCSSWITCH ...
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... ADAV801 Transmitter Message Zeros Most Significant Byte—Address 0001111 (0x0F) Table 43. Transmitter Message Zeros Most Significant Byte Register Bit Map MSBZeros7 MSBZeros6 MSBZeros5 Table 44. Transmitter Message Zeros Most Significant Byte Register Bit Description Bit Name Description MSBZeros[7:0] Most significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). ...
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... Preamble-C of Channel SRCRATIO04 SRCRATIO03 SRCRATIO02 PRE_C12 PRE_C11 PRE_C10 PRE_C04 PRE_C03 PRE_C02 PRE_D12 PRE_D11 PRE_D10 PRE_D04 PRE_D03 PRE_D02 Rev Page ADAV801 1 0 SRCRATIO01 SRCRATIO00 1 0 PRE_C9 PRE_C8 1 0 PRE_C01 PRE_C00 1 0 PRE_D9 PRE_D8 1 0 PRE_D01 PRE_D00 ...
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... ADAV801 Receiver Error—Address 0011000 (0x18) Table 61. Receiver Error Register (Read-Only) Bit Map RxValidity Emphasis NonAudio Table 62. Receiver Error Register (Read-Only) Bit Descriptions Bit Name Description RxValidity This is the VALIDITY bit in the AES3 received stream. Emphasis This bit is set if the audio data is pre-emphasized. Once it has been read, it remains high and does not generate an interrupt unless it changes state ...
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... OVRR bit generates an interrupt. Reserved. MUTE_IND MASK Masks the MUTE_IND from generating an interrupt MUTE_IND bit does not generate an interrupt MUTE_IND bit generates an interrupt Reserved TOO_SLOW OVRL Reserved Reserved OVRL Mask Rev Page ADAV801 1 0 OVRR MUTE_IND 1 0 OVRR Mask MUTE_IND MASK ...
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... ADAV801 Interrupt Status—Address 0011100 (0x1C) Table 69. Interrupt Status Register Bit Map SRCError TxCSTINT TxUBINT Table 70. Interrupt Status Register Bit Descriptions Bit Name Description SRCError This bit is set if one of the sample rate converter interrupts is asserted, and the host should immediately read the sample rate converter error register ...
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... Reserved Reserved SRC_DEEM1 Reserved DTS-CD NonAudio Preamble Frame RCSB4 RCSB3 RCSB2 TCSB4 TCSB3 TCSB2 Rev Page ADAV801 1 0 SRC_DEEM0 Reserved 1 0 NonAudio NonAudio Subframe_A Subframe_B 1 0 RCSB1 RCSB0 1 0 TCSB1 TCSB0 ...
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... ADAV801 Receiver User Bit Buffer Indirect Address— Address 1010000 (0x50) Table 81. Receiver User Bit Buffer Indirect Address Register Bit Map RxUBADDR7 RxUBADDR6 RxUBADDR5 Table 82. Receiver User Bit Buffer Indirect Address Register Bit Descriptions Bit Name Description RxUBADDR[7:0] Indirect address pointing to the address location in the receiver user bit buffer. ...
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... Absolute Absolute Absolute second second second Absolute Absolute Absolute frame frame frame 4 3 REC1 REC0 Rev Page ADAV801 Bit 2 Bit 1 Bit 0 Control Control Control Track Track Track number number number Index Index Index Minute Minute Minute Second ...
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... ADAV801 Datapath Control Register 2—Address 1100011 (0x63) Table 94. Datapath Control Register 2 Bit Map Reserved Reserved DAC2 Table 95. Datapath Control Register 2 Bit Descriptions Bit Name Description DAC[2:0] Datapath source select for DAC ADC DIR Playback Auxiliary in. 100 = SRC. DIT[2:0] Datapath source select for DIT. ...
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... DAC zero flag on mute and zero volume Enabled Disabled. ZFDATA DAC zero flag on zero data disable Enabled Disabled. ZFPOL DAC zero flag polarity Active low Active high DMCLK0 DFS1 DFS0 ). Reserved Reserved ZFVOL Rev Page ADAV801 1 0 DEEM1 DEEM0 1 0 ZFDATA ZFPOL ...
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... ADAV801 DAC Control Register 4—Address 1100111 (0x67) Table 102. DAC Control Register 4 Bit Map Reserved INTRPT ZEROSEL1 Table 103. DAC Control Register 4 Bit Descriptions Bit Name Description INTRPT This bit selects the functionality of the ZEROL/INT pin Pin functions as a ZEROL flag pin. ...
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... AGR[5:0] PGA right channel gain control. 000000 = 0 dB. 000001 = 0.5 dB. … 101111 = 23.5 dB. 110000 = 24 dB. … 111111 = 24 dB DRP4 DRP3 DRP2 AGL4 AGL3 AGL2 AGR4 AGR3 AGR2 Rev Page ADAV801 1 0 DRP1 DRP0 1 0 AGL1 AGL0 1 0 AGR1 AGR0 ...
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... ADAV801 ADC Control Register 1—Address 1101110 (0x6E) Table 116. ADC Control Register 1 Bit Map AMC HPF PWRDWN Table 117. ADC Control Register 1 Bit Descriptions Bit Name Description AMC ADC modulator clock ADC MCLK/2 (128 × ADC MCLK/4 (64 × f HPF High-pass filter enable ...
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... ADC right channel peak volume detection. 000000 = 0 dBFS. 000001 = −1 dBFS. 111111 = −63 dBFS AVOLL4 AVOLL3 AVOLL2 AVOLR4 AVOLR3 AVOLR2 ALP4 ALP3 ALP2 ARP4 ARP3 ARP2 Rev Page ADAV801 1 0 AVOLL1 AVOLL0 1 0 AVOLR1 AVOLR0 1 0 ALP1 ALP0 1 0 ARP1 ARP0 ...
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... ADAV801 PLL Control Register 1—Address 1110100 (0x74) Table 128. PLL Control Register 1 Bit Map DIRIN_CLK1 DIRIN_CLK0 MCLKODIV Table 129. PLL Control Register 1 Bit Descriptions Bit Name Description DIRIN_CLK[1:0] Recovered S/PDIF clock sent to SYSCLK3 SYSCLK3 comes from PLL block Reserved Reserved. ...
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... Sample rate select for PLL1 kHz Reserved kHz 44.1 kHz. SEL1 Oversample ratio select for PLL1 256 × 384 × DOUB1 Double-selected sample rate on PLL1 Disabled Enabled DOUB2 FS1 FS0 Rev Page ADAV801 1 0 SEL1 DOUB1 ...
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... ADAV801 Internal Clocking Control Register 1—Address 1110110 (0x76) Table 132. Internal Clocking Control Register 1 Bit Map DCLK2 DCLK1 DCLK0 Table 133. Internal Clocking Control Register 1 Bit Descriptions Bit Name Description DCLK[2:0] DAC clock source select. 000 = XIN. 001 = MCLKI. 010 = PLLINT1. ...
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... DIRIN accepts input signals as defined in the Specifications section. SYSCLK1 Enables the SYSCLK1 output Enabled Disabled. SYSCLK2 Enables the SYSCLK2 output Enabled Disabled. SYSCLK3 Enables the SYSCLK3 output Enabled Disabled Reserved Reserved Reserved DIRIN_PIN Reserved SYSCLK1 Rev Page ADAV801 1 0 Reserved Reserved 1 0 SYSCLK2 SYSCLK3 ...
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... ADAV801 ALC Control Register 1—Address 1111011 (0x7B) Table 140. ALC Control Register 1 Bit Map FSSEL1 FSSEL0 GAINCNTR1 Table 141. ALC Control Register 1 Bit Descriptions Bit Name Description FSSEL[1:0] These bits should equal the sample rate of the ADC kHz kHz. ...
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... A write to this register restarts the ALC operation. The value written to this register is irrelevant. A read from this register gives the gain reduction factor ATKTH1 ATKTH0 RECTIME1 ALC RESET ALC RESET ALC RESET Rev Page ADAV801 1 0 RECTIME0 ATKTIME 1 0 ALC RESET ALC RESET ...
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... XIN and XOUT pins is still active, so that a stable clock source is available when the ADAV801 is taken out of reset. In addition, the VCO associated with the S/PDIF receiver is active so that the receiver locks to the incoming S/PDIF stream in the shortest possible time ...
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... Figure 57. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters Control Interface DAC Outputs Package Description SPI Single-Ended 64-Lead Low Profile Quad Flat Package [LQFP] SPI Single-Ended 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Rev Page ADAV801 49 48 10.20 10. 0.27 0.22 0.17 Package Option ST-64-2 ST-64-2 ...
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... ADAV801 NOTES ©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04577-0-7/07(A) Rev Page ...