adau1361 Analog Devices, Inc., adau1361 Datasheet - Page 44

• Manufacturer Part Number: adau1361
• Description: Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll
• Manufacturer: Analog Devices, Inc.

ADAU1361
CONTROL REGISTER DETAIL
All registers except for the PLL con
R0: Clock Control 1638
Bit 7
Table 27. Clock Control Register
Bit
3
[2:1]
0
R1: PLL Control 16386 (0x4002)
Byte
0
1
2
3
4
5
Table
Byte
0
1
2
3
28. PLL ontrol Register
Bit
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
CLKSRC
INF Q[1:0]
COREN
RE
C
B
R
eserved
Bit 6
it 7
Bit Name
M[15:8]
M[7:0]
N[15:8]
N[7:0]
4 (0x4000)
Description
Clock source select.
0 = dire
1 = PLL clock.
Inpu
automa
Setting
00
01
10
11
Core clock en
0 = core clock disabled (d
1 = core clock enabled.
Reserved
Bit 6
t cloc
trol register are one-byte write and read registers.
ct from MCLK pin (default).
tically se
Bit 5
S
D
PLL denominator MSB. This va
PLL denominator LSB. This va
M[15:8] (MSB)
00000000
…
00000000
…
1111
PLL numerator MSB. This value is concatena
PLL numer
N[15:8
00000000
…
00000000
…
11111111
escription
k frequenc
1111
able. Only the
] (MSB)
t to 1024 × f
ator LSB
Bit 5
y. Sets the c
B t 4
efault).
i
. This value is
R0 and R1 regis
S
.
Reserved
R[3:0]
Input Clock Frequency
256 × f
512 × f
768 × f
1024 × f
ore clock ra
Rev. 0 | Page 44 of 80
Bit
M[7:0] (LSB)
00000000
…
111111
…
1111
N
00000000
…
00001100
…
11111111
lue is concatena
lue is concat
[7:0] (LSB)
S
S
S
4
(default)
S
concatenated with N[15:8] to m
1111
ters can be ac
Bit 3
CLKSRC
te that generates the co
01
M[15:8]
N[15:8]
M[7:0]
N[7:0]
enated with M[7:0] to make u
Bit 3
ted with N[7:0] t
ted with M[15:8] to make
cessed when this bit i
Bit
Value of M
0
…
2
…
65535
Value o
0
…
12 (default)
…
65535
2
53 (default)
Bit 2
re clock. If t
o make up a 16-bit number.
INFREQ[1:0]
f N
ake up a 16-bit number.
s set to 0 (co
X[1:0]
Bit 1
he PLL is us
up a 16
p a 16-
Bit 1
Lock
-bit
bit n
number.
ed, this v
re clock disa
umber.
B
COREN
it 0
Bit
Type
PLLEN
alu
0
e is
bled).