adau1361 Analog Devices, Inc., adau1361 Datasheet - Page 22

• Manufacturer Part Number: adau1361
• Description: Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll
• Manufacturer: Analog Devices, Inc.

ADAU1361
STARTUP, INITIALIZATION
This section describes the procedure for properly starting up
the ADAU1361. The following sequence provides a high level
approach to the proper initiation of the system.
1.
2.
3.
4.
POWER-UP SEQUENCE
The ADAU1361 uses a power-on reset (POR) circuit to
reset the registers upon power-up. The POR monitors the
DVDDOUT pin and generates a reset signal whenever power
is applied to the chip. During the reset, the ADAU1361 is set
to the default values documented in the register map (see the
Control Registers section). Typically, with a 10 μF capacitor on
AVDD, the POR takes approximately 14 ms.
The PLL lock time is dependent on the MCLK rate. Typical lock
times are provided in Table 11.
Table 11. PLL Lock Time
PLL Mode
Fractional
Fractional
Integer
Fractional
Fractional
Fractional
Fractional
Fractional
Fractional
Integer
Fractional
Fractional
DVDDOUT
AVDD
POR
Apply power to the ADAU1361.
Lock the PLL with the input clock (if using the PLL).
Enable the core clock.
Load the register s
ACTIVE
POR
Figure 27. Power-On Reset Sequence
POR
FINISHED
MCLK Frequency
8 MHz
12 MHz
12.288 MHz
13 MHz
14.4 MHz
19.2 MHz
19.68 MHz
19.8 MHz
24 MHz
24.576 MHz
26 MHz
27 MHz
1.35V
ettings.
PART READY
1.5V
, AND POWER
Lock Time (Typical)
3.5 ms
3.0 ms
2.96 ms
2.4 ms
2.4 ms
2.98 ms
2.98 ms
2.98 ms
2.95 ms
2.96 ms
2.4 ms
2.4 ms
0.95V
POR ACTIVE
Rev. 0 | Page 22 of 80
POWER REDUCTION MODES
Sections of the ADAU1361 chip can be turned on and off as
needed to reduce power consumption. These include the ADCs,
the DACs, and the PLL.
In addition, the control registers can be used to configure some
functions for power saving, normal, or enhanced performance
operation. See the Control Registers section for more information.
DIGITAL POWER SUPPLY
The digital power supply for the ADAU1361 is generated fr
an internal regulator. This regulator generates a 1.5 V supply
internally. The only external connection to this regulator is the
DVDDOUT bypassing point. A 100 nF capacitor and a 10 μF
capacitor should be connected between this pin and DGN
INPUT/OUTPUT POWER SUPPLY
The power for the digital output pins is supplied from IOVDD
and this pin also sets the highest input voltage that should be
seen on the digital input pins. IOVDD should be s
1.8 V and 3.3 V; no digital input signal should be at a voltage
level higher than the one on IOVDD. Th
p
outputs. IOVDD should be decoupled to DGND with a 100 nF
capacitor and a 10 μF capacitor.
CLOCK GENERATION AND MANAGEMENT
The ADAU1361 uses a flexible clocking scheme that enables the
use of many different input clock rates. The PLL can be bypassed
or used, resulting in two different approaches to clock manage-
ment. For more information about clocking schemes, PLL
configuration, and sampling rates, see the Clocking and
Sampling Rates section.
Case 1: PLL Is Bypassed
If the PLL is bypassed, the core clock is derived directly from
the MCLK input. The rate of this clock must be set properly in
Register R0 (clock control register, Address 0x4000) using the
INFREQ[1:0] bits. When the PLL is bypassed, supported
external clock rates are 256 × f
where f
off until the core clock enable bit (COREN) is asserted.
Case 2: PLL Is Used
The core clock to the entire chip is off during the PLL lock
acquisition period. The user can poll the lock bit to determine
when the PLL has locked. After lock is acquired, the ADAU1361
can be started by asserting the core clock enable bit (COREN)
in Register R0 (clock control register, Address 0x4000). This bit
enables the core clock to all the internal blocks of the ADAU1361.
in is variable because it depends on the loads of the digital
S
is the base sampling rate. The core clock of the chip is
S
, 512 × f
S
, 768 × f
e current draw of this
S
, and 1024 × f
et between
D.
om
,
S
,