tspc860 ATMEL Corporation, tspc860 Datasheet - Page 65

• Manufacturer Part Number: tspc860
• Description: Integrated Communication Processor
• Manufacturer: ATMEL Corporation

Table 19. Serial Interface AC Electrical Specifications
Notes:
2129B–HIREL–12/04
Number
71A
78A
80A
83A
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
1. The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
2. Where P = 1/CLKOUT. Thus for a 25 MHz CLKO1 rate, P = 40 ns.
3. These specs are valid for IDL mode only.
4. The strobes and T × D on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes later.
Characteristic
L1RCLK, L1TCLK Frequency (DSC = 0)
L1RCLK, L1TCLK Width Low (DSC = 0)
L1RCLK, L1TCLK Width High (DSC = 0)
L1TXD, L1ST(1-4), L1RQ, L1CLKO Rise/Fall Time
L1RSYNC, L1TSYNC Valid to L1CLK Edge (SYNC Setup Time)
L1CLK Edge to L1RSYNC, L1TSYNC Invalid (SYNC Hold Time)
L1RSYNC, L1TSYNC Rise/Fall Time
L1RXD Valid to L1CLK Edge (L1RXD Setup Time)
L1CLK Edge to L1RXD Invalid (L1RXD Hold Time)
L1CLK Edge to L1ST(1-4) Valid
L1SYNC Valid to L1ST(1-4) Valid
L1CLK Edge to L1ST(1-4) Invalid
L1CLK Edge to L1TXD Valid
L1TSYNC Valid to L1TXD Valid
L1CLK Edge to L1TXD High Impedance
L1RCLK, L1TCLK Frequency (DSC = 1)
L1RCLK, L1TCLK Width Low (DSC = 1)
L1RCLK, L1TCLK Width High (DSC = 1)
L1CLK Edge to L1CLKO Valid (DSC = 1)
L1RQ Valid Before Falling Edge of L1TSYNC
L1GR Setup Time
L1GR Hold Time
L1CLK Edge to L1SYNC Valid (FSD = 00, CNT = 0000, BYT = 0,
DSC = 0)
(3)
(4)
(4)
(1)(3)
(3)
(2)
(2)
(4)
P+10
P+10
P+10
P+10
Min
20
35
17
13
10
10
10
10
10
42
42
–
–
–
0
–
–
1
–
All Frequencies
16 or SYNCCLK/2
SYNCCLK/2.5
Max
15
15
45
45
45
55
55
42
30
–
–
–
–
–
–
–
–
–
–
0
L1TCLK
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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