tspc860 ATMEL Corporation, tspc860 Datasheet - Page 14

• Manufacturer Part Number: tspc860
• Description: Integrated Communication Processor
• Manufacturer: ATMEL Corporation

Table 1. Signal Descriptions (Continued)
14
GPL_A(2-3)
GPL_B(2-3)
RSTCONF
PORESET
UPWAITB
UPWAITA
HRESET
GPL_A0
GPL_B0
GPL_A1
GPL_B1
GPL_A4
GPL_B4
GPL_A5
CS(2-3)
Name
OE
TSPC860 [Preliminary]
Reset
High
High
High
High
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Low
Number
B5, C5
D7
C6
C1
D3
R2
N4
B1
P3
Bidirectional
Bidirectional
Open-drain
Output
Output
Output
Output
Type
Input
Input
Description
General-Purpose Line 0 on UPMA—This output reflects the value
specified in the UPMA when an external transfer to a slave is
controlled by the UPMA.
General-Purpose Line 0 on UPMB—This output reflects the value
specified in the UPMB when an external transfer to a slave is
controlled by the UPMB.
Output Enable—Output asserted when the TSPC860 initiates a read
access to an external slave controlled by the GPCM.
General-Purpose Line 1 on UPMA—This output reflects the value
specified in the UPMA when an external transfer to a slave is
controlled by UPMA.
General-Purpose Line 1 on UPMB—This output reflects the value
specified in the UPMB when an external transfer to a slave is
controlled by UPMB.
General-Purpose Line 2 and 3 on UPMA—These outputs reflect the
value specified in the UPMA when an external transfer to a slave is
controlled by UPMA.
General-Purpose Line 2 and 3 on UPMB—These outputs reflect the
value specified in the UPMB when an external transfer to a slave is
controlled by UPMB.
Chip Select 2 and 3—These outputs enable peripheral or memory
devices at programmed addresses if they are appropriately defined.
The double drive capability for CS2 and CS3 is independently
defined for each signal in the SIUMCR.
User Programmable Machine Wait A—This input is sampled as
defined by the user when an access to an external slave is controlled
by the UPMA.
General-Purpose Line 4 on UPMA—This output reflects the value
specified in the UPMA when an external transfer to a slave is
controlled by UPMA.
User Programmable Machine Wait B—This input is sampled as
defined by the user when an access to an external slave is controlled
by the UPMB.
General-Purpose Line 4 on UPMB—This output reflects the value
specified in the UPMB when an external transfer to a slave is
controlled by UPMB.
General-Purpose Line 5 on UPMA—This output reflects the value
specified in the UPMA when an external transfer to a slave is
controlled by UPMA. This signal can also be controlled by the
UPMB.
Power on Reset—When asserted, this input causes the TSPC860 to
enter the power-on reset state.
Reset Configuration—The TSPC860 samples this input while
HRESET is asserted. If RSTCONF is asserted, the configuration
mode is sampled in the form of the hard reset configuration word
driven on the data bus. When RSTCONF is negated, the TSPC860
uses the default configuration mode. Note that the initial base
address of internal registers is determined in this sequence.
Hard Reset—Asserting this open drain signal puts the TSPC860 in
hard reset state.
2129B–HIREL–12/04