tspc860 ATMEL Corporation, tspc860 Datasheet - Page 16

• Manufacturer Part Number: tspc860
• Description: Integrated Communication Processor
• Manufacturer: ATMEL Corporation

Table 1. Signal Descriptions (Continued)
16
DSCK/AT1
VFLS(0-1)
IOIS16_B
IP_B(0-1)
IWP(0-1)
ALE_B
Name
IP_B2
IP_B3
IP_B4
LWP0
IWP2
VF2
VF0
AT2
TSPC860 [Preliminary]
States During
States During
States During
See Section
See Section
See Section
Hardware
Reset” on
Hardware
Reset” on
Hardware
Reset” on
page 27
page 27
page 27
“Signal
“Signal
“Signal
Reset
Hi-Z
Hi-Z
Number
H2, J3
G1
G2
J1
J2
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Three-state
Three-state
Type
Description
Address Latch Enable B—This output is asserted when the
TSPC860 initiates an access to a region under the control of the
PCMCIA socket B interface.
Development Serial Clock—This input is the clock for the debug port
interface.
Address Type 1—The TSPC860 drives this bidirectional three-state
line when it initiates a transaction on the external bus. When the
transaction is initiated by the core, it indicates if the transfer is for
user or supervisor state. This signal is not used for transactions
initiated by external masters.
Input Port B 0-1—The TSPC860 senses these inputs; their values
and changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Instruction Watchpoint 0-1—These outputs report the detection of an
instruction watchpoint in the program flow executed by the core.
Visible History Buffer Flushes Status—The TSPC860 outputs
VFLS(0-1) when program instruction flow tracking is required. They
report the number of instructions flushed from the history buffer in
the core.
Input Port B 2—The TSPC860 senses this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
I/O Device B is 16- Bits Port Size—The TSPC860 monitors this input
when a PCMCIA interface transaction is initiated to an I/O region in
socket B in the PCMCIA space.
Address Type 2—The TSPC860 drives this bidirectional three-state
signal when it initiates a transaction on the external bus. If the core
initiates the transaction, it indicates if the transfer is instruction or
data. This signal is not used for transactions initiated by external
masters.
Input Port B 3 — The TSPC860 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Instruction Watchpoint 2—This output reports the detection of an
instruction watchpoint in the program flow executed by the core.
Visible Instruction Queue Flush Status—The TSPC860 outputs VF2
with VF0/VF1 when instruction flow tracking is required. VFn reports
the number of instructions flushed from the instruction queue in the
core.
Input Port B 4—The TSPC860 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Load/Store Watchpoint 0—This output reports the detection of a
data watchpoint in the program flow executed by the core.
Visible Instruction Queue Flushes Status—The TSPC860 outputs
VF0 with VF1/VF2 when instruction flow tracking is required. VFn
reports the number of instructions flushed from the instruction queue
in the core.
2129B–HIREL–12/04