tspc860 ATMEL Corporation, tspc860 Datasheet - Page 11

• Manufacturer Part Number: tspc860
• Description: Integrated Communication Processor
• Manufacturer: ATMEL Corporation

Table 1. Signal Descriptions (Continued)
2129B–HIREL–12/04
D(0-31)
Name
IRQ3
IRQ4
IRQ5
IRQ6
DP0
DP1
DP2
DP3
BR
pulled down)
Hi-Z (Pulled
RSTCONF
Reset
Low if
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Number
Figure 2
See
W4
G4
V3
V5
V4
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Three-state
Three-state
Three-state
Three-state
Three-state
Type
Description
Data Bus—This bidirectional three-state bus provides the general-
purpose data path between the TSPC860 and all other devices. The
32-bit data path can be dynamically sized to support 8-, 16-, or 32-bit
transfers. D0 is the MSB of the data bus.
Data Parity 0—Provides parity generation and checking for D(0-7) for
transfers to a slave device initiated by the TSPC860. The parity
function can be defined independently for each one of the addressed
memory banks (if controlled by the memory controller) and for the
rest of the slaves sitting on the external bus. Parity generation and
checking is not supported for external masters.
Interrupt Request 3—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core. Note that the interrupt request signal sent to the interrupt
controller is the logical AND of DP0/IRQ3 (if defined as IRQ3) and
CR/IRQ3 (if defined as IRQ3).
Data Parity 1—Provides parity generation and checking for D(8-15)
for transfers to a slave device initiated by the TSPC860. The parity
function can be defined independently for each one of the addressed
memory banks (if controlled by the memory controller) and for the
rest of the slaves on the external bus. Parity generation and checking
is not supported for external masters.
Interrupt Request 4—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core. Note that the interrupt request signal sent to the interrupt
controller is the logical AND of this line (if defined as IRQ4) and
KR/IRQ4/SPKROUT (if defined as IRQ4).
Data Parity 2—Provides parity generation and checking for D(16-23)
for transfers to a slave device initiated by the TSPC860. The parity
function can be defined independently for each one of the addressed
memory banks (if controlled by the memory controller) and for the
rest of the slaves on the external bus. Parity generation and checking
is not supported for external masters.
Interrupt Request 5—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core.
Data Parity 3—Provides parity generation and checking for D(24-31)
for transfers to a slave device initiated by the TSPC860. The parity
function can be defined independently for each one of the addressed
memory banks (if controlled by the memory controller) and for the
rest of the slaves on the external bus. Parity generation and checking
is not supported for external masters.
Interrupt Request 6—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core. Note that the interrupt request signal sent to the interrupt
controller is the logical AND of this line (if defined as IRQ6) and the
FRZ/IRQ6 (if defined as IRQ6).
Bus Request—Asserted low when a possible master is requesting
ownership of the bus. When the TSPC860 is configured to work with
the internal arbiter, this signal is configured as an input. When the
TSPC860 is configured to work with an external arbiter, this signal is
configured as an output and asserted every time a new transaction is
intended to be initiated (no parking on the bus).
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