mpc8378e Freescale Semiconductor, Inc, mpc8378e Datasheet - Page 82

• Manufacturer Part Number: mpc8378e
• Description: Powerquicc Ii Pro Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

High-Speed Serial Interfaces (HSSI)
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(V
between 500 mV and –500 mV, in other words, V
phase. The peak differential voltage (V
is 1000 mV
20.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and
SD1_REF_CLK for both lanes of SerDes1, and SD2_REF_CLK and SD2_REF_CLK for both lanes of
SerDes2.
The following sections describe the SerDes reference clock requirements and some application
information.
20.2.1
Figure 55
82
OD
•
•
) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
SerDes Reference Clock Receiver Reference Circuit Structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
SerDes Reference Clocks
shows a receiver reference diagram of the SerDes reference clocks.
shown in
50 Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
Differential Mode and Single-ended Mode description below for further detailed requirements.
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), since the
input is AC-coupled on-chip.
(0.4 V ÷ 50 = 8 mA) while the minimum common mode input level is 0.1 V above
SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by
a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such
that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the
common mode voltage at 400 mV.
p-p
SerDes Reference Clock Receiver Characteristics
.
p-p
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
, which is referred as the single-ended swing for each signal. In this example, since
Figure
55. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a
DIFFp
) is 500 mV. The peak-to-peak differential voltage (V
OD
is 500 mV in one phase and –500 mV in the other
Freescale Semiconductor
DIFFp-p
)