mpc8378e Freescale Semiconductor, Inc, mpc8378e Datasheet - Page 111

• Manufacturer Part Number: mpc8378e
• Description: Powerquicc Ii Pro Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Table 70
conditions (see
22.1
The system PLL is controlled by the RCWL[SPMF] parameter. The system PLL VCO frequency depends
on RCWL[DDRCM] and RCWL[LBCM].
system PLL.
Freescale Semiconductor
1
2
3
e300 core frequency ( core_clk )
Coherent system bus frequency ( csb_clk )
DDR2 memory bus frequency (MCK)
DDR1 memory bus frequency (MCK)
Local bus frequency (LCLK n )
Local bus controller frequency ( lbc_clk )
PCI input frequency (CLKIN or PCI_CLK)
eTSEC frequency
Security encryption controller frequency
USB controller frequency
eSDHC controller frequency
PCI Express controller frequency
Note:
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[xCM] must be programmed such that the maximum internal operating frequency of the Security core, USB modules,
SATA, and eSDHC will not exceed their respective value listed in this table.
the csb_clk frequency (depending on RCWL[LBIUCM]).
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk , MCK,
The DDR data rate is 2× the DDR memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
provides the operating frequencies for the TePBGA II package under recommended operating
System PLL Configuration
If RCWL[DDRCM] and RCWL[LBCM] are both cleared, the system PLL
VCO frequency = (CSB frequency) × (System PLL VCO Divider).
If either RCWL[DDRCM] or RCWL[LBCM] are set, the system PLL VCO
frequency = 2 × (CSB frequency) × (System PLL VCO Divider).
The VCO divider needs to be set properly so that the System PLL VCO
frequency is in the range of 400–800 MHz.
Table
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
3).
Parameter
3
Table 70. Operating Frequencies for TePBGA II
2
2
1
Table 71
NOTE
shows the multiplication factor encodings for the
Minimum Operating
Frequency (MHz)
333
133
125
167
—
—
25
—
—
—
—
—
Maximum Operating
Frequency (MHz)
800
400
200
333
133
400
400
200
200
200
400
66
Clocking
111