mpc8378e Freescale Semiconductor, Inc, mpc8378e Datasheet - Page 43

• Manufacturer Part Number: mpc8378e
• Description: Powerquicc Ii Pro Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Table 45
bypass mode.
Figure 23
Freescale Semiconductor
Local bus cycle time
Input setup to local bus clock
Input hold from local bus clock
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
Local bus clock to output valid
Local bus clock to output high impedance for LAD/LDP
Note:
1
2
3
4
5
6
7
8
The symbols used for timing specifications herein follow the pattern of t
for inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock one(1). Also, t
output (O) going invalid (X) or output hold time.
All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
All signals are measured from LBV
signaling levels.
Input timings are measured at the pin.
t
output pins.
t
LAD output pins.
t
For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
LBOTOT1
LBOTOT2
LBOTOT3
describes the general timing parameters of the local bus interface of the device when in PLL
provides the AC test load for the local bus.
should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on LAD
should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load on
should be used when LBCR[AHD] is not set and the load on LALE output pin equals to the load on LAD output pins.
(First two letters of functional block)(reference)(state)(signal)(state)
LBKHOX
Table 45. Local Bus General Timing Parameters—PLL Bypass Mode
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
Parameter
Output
symbolizes local bus timing (LB) for the t
DD
/2 of the rising/falling edge of LCLK0 to 0.4 × LBV
Figure 23. Local Bus AC Test Load
Z
0
= 50 Ω
Symbol
t
t
t
t
t
LBOTOT1
LBOTOT2
LBOTOT3
t
t
LBKHOV
LBKHOZ
LBIVKH
LBIXKH
t
LBK
LBK
for outputs. For example, t
1
(First two letters of functional block)(signal)(state) (reference)(state)
LBK
clock reference (K) to go high (H), with respect to the
R
clock reference (K) goes high (H), in this case for
L
= 50 Ω
Min
7.0
1.0
1.5
3.0
2.5
15
—
—
DD
OVDD/2
of the signal in question for 3.3-V
Max
3.0
4.0
—
—
—
—
—
—
LBIXKH1
symbolizes local bus
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Local Bus
Notes
3, 4
3, 4
3, 8
2
5
6
7
3
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