mpc8378e Freescale Semiconductor, Inc, mpc8378e Datasheet - Page 114

• Manufacturer Part Number: mpc8378e
• Description: Powerquicc Ii Pro Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Clocking
1
2
22.2
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
not listed in
114
CFG_CLKIN_DIV doubles csb_clk if set high.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
0–1
nn
11
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
Core PLL Configuration
Table 75
RCWL[COREPLL]
Core VCO frequency = core frequency × VCO divider
VCO divider has to be set properly so that the core VCO frequency is in the
range of 800–1600 MHz.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
nnnn
0000
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
0011
0011
2–5
should be considered as reserved.
Table 75
shows the encodings for RCWL[COREPLL]. COREPLL values that are
Table 75. e300 Core PLL Configuration
6
0
n
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
(PLL off, csb_clk clocks core directly)
core_clk : csb_clk Ratio
NOTE
PLL bypassed
1.5:1
1.5:1
1.5:1
2.5:1
2.5:1
2.5:1
3.5:1
3.5:1
3.5:1
n/a
1:1
1:1
1:1
2:1
2:1
2:1
3:1
3:1
3:1
(PLL off, csb_clk clocks core
Freescale Semiconductor
VCO Divider
PLL bypassed
directly)
n/a
2
4
8
2
4
8
2
4
8
2
4
8
2
4
8
2
4
8
1