mpc850de Freescale Semiconductor, Inc, mpc850de Datasheet - Page 30

• Manufacturer Part Number: mpc850de
• Description: Mpc850 Rev. A/b/c Communications Controller
• Manufacturer: Freescale Semiconductor, Inc

1
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no
Layout Practices
Figure 20 provides the timing for the asynchronous external master memory access controlled by the
GPCM.
Figure 21 provides the timing for the asynchronous external master control signals negation.
Table 7 provides interrupt timing for the MPC850.
30
Figure 20. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
Num
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
direct relation with the total system interrupt latency that the MPC850 is able to support
I39
I40
I41
I42
I43
IRQx valid to CLKOUT rising edge (set up time)
IRQx hold time after CLKOUT.
IRQx pulse width low
IRQx pulse width high
IRQx edge-to-edge time
Figure 21. Asynchronous External Master—Control Signals Negation Timing
Characteristic
MPC850 (Rev. A/B/C) Hardware Specifications
1
Table 7. Interrupt Timing
80.00
6.00
2.00
3.00
3.00
Min
50 MHz
Max
—
—
—
—
—
121.0
6.00
2.00
3.00
3.00
Min
66MHz
Max
—
—
—
—
—
100.0
6.00
2.00
3.00
3.00
Min
80 MHz
MOTOROLA
Max
—
—
—
—
—
Unit
ns
ns
ns
ns
ns