mpc850de Freescale Semiconductor, Inc, mpc850de Datasheet - Page 18

• Manufacturer Part Number: mpc850de
• Description: Mpc850 Rev. A/b/c Communications Controller
• Manufacturer: Freescale Semiconductor, Inc

8
9
10
11
Layout Practices
Figure 2 is the control timing diagram.
18
The D[0:31] and DP[0:3] input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for
read accesses controlled by chip-selects controlled by the UPM in the memory controller, for data beats where DLT3
= 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.
The timing B30 refers to CS when ACS = '00' and to WE[0:3] when CSNT = '0'.
The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in
B37 and B38 are specified to enable the freeze of the UPM output signals.
The AS signal is considered asynchronous to CLKOUT.
CLKOUT
Outputs
Outputs
Inputs
Inputs
C
D
A
B
Maximum output delay specification
Minimum output hold time
Minimum input setup time specification
Minimum input hold time specification
MPC850 (Rev. A/B/C) Hardware Specifications
A
B
Figure 2. Control Timing
MOTOROLA