mc68hc05pl4b Freescale Semiconductor, Inc, mc68hc05pl4b Datasheet - Page 58

• Manufacturer Part Number: mc68hc05pl4b
• Description: Low-cost Single-chip Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

GENERAL RELEASE SPECIFICATION
9.5
9-8
A software example of this procedure is shown in Table 9-1.
TIMER CONTROL REGISTER (TCR)
The timer control register shown in Figure 9-10 performs the following functions:
Reset clears all the bits in the TCR with the exception of the IEDG bit which is
unaffected.
ICIE - INPUT CAPTURE INTERRUPT ENABLE
TCR
$0012
9B
...
...
B7
B6
BF
...
...
9A
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This also
5. Enable interrupts by clearing the I bit in the condition code register.
•
•
•
•
•
•
•
This read/write bit enables interrupts caused by an active signal on the PB1/
TCAP pin or from CPF2 ag bit of the analog subsystem v oltage comparator 2.
Reset clears the ICIE bit.
reset:
1 = Input capture interrupts enabled.
0 = Input capture interrupts disabled.
clears the OCF ag bit in the TSR.
Enables input capture interrupts.
Enables output compare interrupts.
Enables timer over o w interrupts.
Con gure the I/O P ort Pin PA2 as input pin for TCAP signal
Con gure the I/O P ort Pin PA3 as output pin for TCMP signal
Control the active edge polarity of the TCAP signal.
Controls the active level of the TCMP output.
W
R
16
13
17
Table 9-1. Output Compare Initialization Example
BIT 7
ICIE
0
Freescale Semiconductor, Inc.
SEI
...
...
STA
LDA
STX
...
...
CLI
Figure 9-10. Timer Control Register (TCR)
For More Information On This Product,
BIT 6
OCIE
16-BIT PROGRAMMABLE TIMER
0
OCRH
TSR
OCRL
Go to: www.freescale.com
BIT 5
TOIE
April 30, 1998
0
DISABLE INTERRUPTS
.....
.....
INHIBIT OUTPUT COMPARE
ARM OCF FLAG FOR CLEARING
READY FOR NEXT COMPARE, OCF CLEARED
.....
.....
ENABLE INTERRUPTS
BIT 4
0
0
BIT 3
0
0
BIT 2
0
0
IEDG
BIT 1
U
MC68HC05PL4
OLVL
REV 2.0
BIT 0
0