mc68hc912bc32 Freescale Semiconductor, Inc, mc68hc912bc32 Datasheet - Page 163

• Manufacturer Part Number: mc68hc912bc32
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer Registers
13.3.2 Pulse Accumulators
Four 8-bit pulse accumulators with four 8-bit holding registers are associated with the four IC buffered
channels. See
Figure
13-3. A pulse accumulator counts the number of active edges at the input of its
channel.
The user can prevent 8-bit pulse accumulators from counting further than $FF by PACMX control bit in
input control system control register (ICSYS). In this case, a value of $FF means that 255 counts or more
have occurred.
Each pair of pulse accumulators can be used as a 16-bit pulse accumulator. See
Figure
13-4.
For more information on the two modes of operation for the pulse accumulators, see
13.3.2.1 Pulse
Accumulator Latch Mode
and
13.3.2.2 Pulse Accumulator Queue
Mode.
13.3.2.1 Pulse Accumulator Latch Mode
The value of the pulse accumulator is transferred to its holding register when the modulus down-counter
reaches zero, a write $0000 to the modulus counter, or when the force latch control bit ICLAT is written.
At the same time, the pulse accumulator is cleared.
13.3.2.2 Pulse Accumulator Queue Mode
When queue mode is enabled, reads of an input capture holding register will transfer the contents of the
associated pulse accumulator to its holding register. At the same time, the pulse accumulator is cleared.
13.3.3 Modulus Down-Counter
The modulus down-counter can be used as a timebase to generate a periodic interrupt. It can also be
used to latch the values of the IC registers and the pulse accumulators to their holding registers. The
action of latching can be programmed to be periodic or only once.
13.4 Timer Registers
Input/output pins default to general-purpose input/output (I/O) lines until an internal function which uses
that pin is specifically enabled. The timer overrides the state of the DDR to force the I/O state of each
associated port line when an output compare using a port line is enabled. In these cases, the data
direction bits will have no effect on these lines.
When a pin is assigned to output an on-chip peripheral function, writing to this PORTT bit does not affect
the pin. The data is stored in an internal latch such that if the pin becomes available for general-purpose
output, the driven level will be the last value written to the PORTT bit.
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor
163