mc68hc908gp20 Freescale Semiconductor, Inc, mc68hc908gp20 Datasheet - Page 332

• Manufacturer Part Number: mc68hc908gp20
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

20.10 Resetting the SPI
Advance Information
332
The following sources in the SPI status and control register can generate
CPU interrupt requests:
Any system reset completely resets the SPI. Partial resets occur
whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the
following occurs:
These items are reset only by a system reset:
By not resetting the control bits when SPE is low, the user can clear SPE
between transmissions without having to set all control bits again when
SPE is set back high for the next transmission.
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SPI receiver full bit (SPRF) — The SPRF bit becomes set every
time a byte transfers from the shift register to the receive data
register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF generates an SPI receiver/error CPU interrupt request.
SPI transmitter empty (SPTE) — The SPTE bit becomes set every
time a byte transfers from the transmit data register to the shift
register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE generates an SPTE CPU interrupt request.
The SPTE flag is set.
Any transmission currently in progress is aborted.
The shift register is cleared.
The SPI state counter is cleared, making it ready for a new
complete transmission.
All the SPI port logic is defaulted back to being general-purpose
I/O.
All control bits in the SPCR register
All control bits in the SPSCR register (MODFEN, ERRIE, SPR1,
and SPR0)
The status flags SPRF, OVRF, and MODF
MC68HC908GP20
Freescale Semiconductor
—
Rev 2.1