mc68hc908gp20 Freescale Semiconductor, Inc, mc68hc908gp20 Datasheet - Page 210

• Manufacturer Part Number: mc68hc908gp20
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

Advance Information
210
NOTE:
PTC3 pin low when entering monitor mode causes a bypass of a divide-
by-two stage at the oscillator only if V
the CGMOUT frequency is equal to the CGMXCLK frequency, and the
OSC1 input directly generates internal bus clocks. In this case, the
OSC1 signal must have a 50% duty cycle at maximum bus frequency.
If entering monitor mode without high voltage on IRQ (above condition
set 2 or 3, where applied voltage is either V
requirements and conditions, including the PTC3 frequency divisor
selection, are not in effect. This is to reduce circuit requirements when
performing in-circuit programming.
If the reset vector is blank and monitor mode is entered, the chip will see
an additional reset cycle after the initial POR reset. Once the part has
been programmed, the traditional method of applying a voltage, V
IRQ must be used to enter monitor mode.
The COP module is disabled in monitor mode based on these
conditions:
The second condition states that as long as V
IRQ pin after entering monitor mode, or if V
the initial reset to get into monitor mode (when V
then the COP will be disabled. In the latter situation, after V
to the RST pin, V
freeing the IRQ for normal functionality in monitor mode.
Figure 15-2
the reset vector is blank and just 1 x V
pin. An external oscillator of 9.8304 MHz is required for a baud rate of
9600, as the internal bus frequency is automatically set to the external
frequency divided by four.
•
•
If monitor mode was entered as a result of the reset vector being
blank (above condition set 2 or 3), the COP is always disabled
regardless of the state of IRQ or RST.
If monitor mode was entered with V
then the COP is disabled as long as V
or RST.
shows a simplified diagram of the monitor mode entry when
TST
can be removed from the IRQ pin in the interest of
TST
DD
is applied to IRQ. In this event,
voltage is applied to the IRQ
TST
DD
TST
TST
or V
on IRQ (condition set 1),
TST
MC68HC908GP20
TST
is applied to RST after
is applied to either IRQ
SS
is maintained on the
Freescale Semiconductor
was applied to IRQ),
), then all port C pin
TST
is applied
—
TST
Rev 2.1
, to